RET Oscilloscope Clock Recovery Using Pattern-Waveform Equalization
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Solution Overview
Problem
Existing real-equivalent-time (RET) oscilloscopes suffer from aliasing due to low sample rates, limiting the accuracy of clock data recovery (CDR) for high-speed signaling applications, and traditional software equalizers cannot effectively compensate for signal impairments.
Innovation Solution
An improved method for software clock data recovery using software equalizers that apply equalization to pattern waveforms, adjusting sample values, and iteratively refining the recovered clock to reduce aliasing and improve accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional software equalizers are used in RET oscilloscopes, then device complexity is reduced, but measurement precision deteriorates due to inability to effectively compensate for signal impairments
Solution Approach 1:
The patent divides the equalization process into multiple stages: first applying a feed-forward equalizer (FFE) to compensate for inter-symbol interference, then using a decision-directed equalizer to further refine the signal. This segmentation allows traditional simple equalizers to be combined in a sequence that achieves superior clock recovery accuracy without requiring a single complex equalizer design
Solution Approach 2:
The patent applies preliminary equalization using FFE before the main clock data recovery process. By pre-compensating for signal impairments such as intersymbol interference in the received signal, the subsequent CDR operation works with already-conditioned data, improving overall measurement precision while keeping individual equalizer components relatively simple
2Productivity
If low sample rates are used in RET oscilloscopes, then productivity is improved through equivalent-time sampling, but measurement precision deteriorates due to aliasing effects
Solution Approach 1:
The patent implements a feedback mechanism where the equalized signal is used to generate expected signal values, which are then compared with actual received samples. The difference (error) is fed back to adjust the equalizer coefficients iteratively. This feedback loop allows the system to compensate for aliasing effects by continuously refining the equalization based on actual signal characteristics, thereby improving measurement precision while maintaining low sample rates
Solution Approach 2:
The patent replaces the need for high-speed hardware sampling (mechanical/system constraint) with software-based equalization and signal processing. Instead of increasing the physical sample rate to avoid aliasing, the system uses digital signal processing techniques to reconstruct and correct the signal, substituting computational methods for hardware limitations
Data Source
AI summary
A test and measurement instrument has an input to receive a signal under test having a repeating pattern. one or more analog-to-digital converters (ADC) to sample the signal under test at a sample rate over many repeating patterns to digitize the signal, one or more processors configured to execute code to cause the one or more processors to: recover a clock from the sampled signal under test, use the clock to generate an original pattern waveform, interpolate and resample from the original pattern waveform to generate an evenly time-spaced pattern waveform, apply an equalizer to the evenly time-spaced pattern waveform to produce an equalized pattern waveform, interpolate and resample from the equalized pattern waveform to produce a new waveform having equalized samples at sample times of the sampled signal under test, recover an updated clock from the new waveform, and use the updated clock to produce an updated waveform.