Retention Clamp Control for Fast Low-Power Wake-Up
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Solution Overview
Problem
Existing power supply generators and regulators face challenges in providing stable and fast power adjustments across a wide leakage load current range, especially during transitions between different power states, due to di/dt and reliability constraints.
Innovation Solution
The implementation of an all-digital closed-loop retention clamp system using a ring-oscillator voltage sensor and a bang-bang controller, which adapts the power gate control to manage voltage slope and error, enabling efficient power state transitions and wake-up from low power states like C1LP and C6.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the processor enters ultra-low power state C6 to eliminate leakage power, then power savings are improved, but exit time and entry time increase due to state copy and restore operations
Solution Approach 1:
The patent performs preliminary actions by pre-copying processor state to retention memory before entering C6 state and pre-restoring state upon exit. The state copy operation is initiated before the actual power state transition, and the restore operation begins before full power restoration, overlapping these operations with the power state transition to reduce total exit time.
Solution Approach 2:
The patent dynamically adjusts the retention voltage level based on the processor's operational needs and transition state. During C6 state transitions, the retention voltage is dynamically controlled to maintain stability while minimizing power consumption, and during exit, the voltage is dynamically restored to enable fast state recovery without full power cycle.
2Use of energy by moving object
If the processor enters low power state C1 with clock gating to save dynamic capacitance, then power consumption is reduced, but leakage power savings are not achieved
Solution Approach 1:
The patent merges the advantages of C1 and C6 states by implementing a C1LP (Low Power) state that combines clock gating with leakage power management. The power gate is controlled to enable both clock gating for dynamic capacitance savings and leakage current suppression, effectively merging the power-saving mechanisms of both states into a single operational mode.
Solution Approach 2:
The patent changes the operational parameters of the power gate by adjusting its control voltage to operate in an intermediate mode between full ON (C0) and full OFF (C6). The power gate control voltage is modulated to achieve partial conduction that simultaneously reduces dynamic capacitance charging and limits leakage current, creating a new operational parameter regime.
3Ease of operation
If gated supply voltage is increased from retention Vmin to active Vmin during power state exit, then processor functionality is restored, but di/dt constraints and reliability issues arise due to sudden charging current increase
Solution Approach 1:
The patent performs preliminary voltage ramping by gradually increasing the retention voltage before full power restoration. The voltage is increased in controlled steps with predefined slopes, allowing the power gate and associated circuits to adapt progressively. This preliminary voltage adjustment prevents sudden current spikes by spreading the charging current increase over an extended time period.
Solution Approach 2:
The patent dynamically controls the voltage transition profile by adjusting the voltage slope based on real-time monitoring of current draw and system state. The voltage ramp rate is dynamically modified to maintain di/dt within safe limits while minimizing total transition time, creating an adaptive voltage restoration process that responds to instantaneous system conditions.
4Stability of the object's composition
If existing power supply generators and regulators are used to provide stable power adjustment, then power stability is maintained, but fast power adjustment and stability across wide leakage load current range are challenging
Solution Approach 1:
The patent pre-configures the power gate control voltage to anticipated power state transitions, preparing the system in advance for upcoming changes. The control voltage is adjusted beforehand based on predicted workload and power state requirements, allowing the power supply to transition more rapidly without compromising stability during the actual transition event.
Solution Approach 2:
The patent implements feedback control by continuously monitoring the power gate current, voltage, and system state, then adjusting the control voltage accordingly. The feedback loop detects changes in leakage load current and power state transitions, dynamically modifying the power gate control to maintain stability while enabling fast adjustment. The feedback mechanism ensures that voltage and current remain within safe operating limits during rapid transitions.
Data Source
AI summary
Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).