Retention Flip-Flop with Clock-Free Single-Pin Data Hold

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Solution Overview

Problem

Integrated circuits with flip-flops experience high power dissipation due to continuous power supply to retain data values, especially when a large number of flip-flops are maintained in a static condition, leading to significant leakage currents.

Innovation Solution

A retention flip-flop design with a single retention control pin that transitions to a clock-free mode, using a primary supply voltage for standard operation and a secondary supply voltage for data retention, allowing the flip-flop to maintain data without generating a clock signal, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If continuous power is supplied to all flip-flop circuitry to retain data values, then data retention is maintained, but power dissipation increases significantly

Engineering Contradiction:

Improvedata retentionVSAvoidpower dissipation

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The flip-flop circuit is segmented into two distinct latches: a first latch that retains data values and a second latch that is disabled during retention mode. This segmentation allows selective power management where only the essential data retention function remains active, significantly reducing power dissipation while maintaining data integrity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention extracts and isolates the essential data retention function into a dedicated first latch, separating it from the full flip-flop circuitry. During retention mode, non-essential circuitry (second latch and associated logic) is taken out of operation, reducing power consumption while preserving the core data retention capability.

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If all flip-flop circuitry remains active to maintain static condition, then data values are preserved, but leakage currents increase

Engineering Contradiction:

Improvedata preservationVSAvoidleakage currents

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The circuit is divided into active and inactive segments during retention mode. The first latch segment remains active to preserve data, while the second latch segment is deactivated. This segmentation minimizes leakage currents by ensuring only essential circuit elements remain powered, reducing the total harmful leakage across the entire flip-flop structure.

Inventive Principle:

Principle #1Segmentation

3Device complexity

If a single retention control pin is used to enable clock-free mode, then device complexity is reduced, but control functionality must be multiplexed

Engineering Contradiction:

Improvecontrol pinsVSAvoidmode control

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The single retention control pin is designed with multi-functionality to manage multiple operations: it controls the transition between standard and retention modes, manages power supply to different latches, and coordinates clock signal generation. This universal control approach reduces device complexity by eliminating the need for separate control pins for each function while maintaining full adaptability through sophisticated internal control logic.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12537516B2Single pin clock-free retention flip-flop

Publication Date: 2026.01.27 STMICROELECTRONICS INT NV

AI summary

A retention flip flop includes a first latch, a second latch, and a retention latch. The first and second latches are powered by an interruptible primary supply voltage while the retention latch is powered by a secondary supply voltage that is not interrupted. The retention flip-flop receives a single retention control signal that controls whether the flip-flop is in a standard mode or a retention mode. In the retention mode, the flip-flop clock signal is paused.