Retention Flip-Flop Control Architecture for Power Collapse Timing
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Solution Overview
Problem
Conventional retention flip-flops are not robust enough to operate in accelerated processing environments, preventing the use of power-conserving benefits in these settings due to clock-clamping conflicts and spurious clock edges when combined with non-retention flip-flops.
Innovation Solution
Implementing a unified control scheme that allows positive-edge-triggered and negative-edge-triggered retention flip-flops to operate together by using a dual power-rail environment and a control signal manager to combine clock and retention signals, enabling efficient data retention and accelerated processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional retention flip-flops are used in accelerated processing environments, then data retention capability is provided, but clock-clamping conflicts and spurious clock edges occur
Solution Approach 1:
The patent segments the control signals for positive-edge-triggered and negative-edge-triggered retention flip-flops into separate pathways. Each flip-flop type receives its own dedicated control signals (CLK_POS_RET for positive-edge, CLK_NEG_RET for negative-edge), preventing signal interference and eliminating clock-clamping conflicts while maintaining data retention capability during power collapse events.
2Use of energy by moving object
If power collapse is implemented to reduce power consumption, then energy savings are achieved, but operational data may be lost
Solution Approach 1:
The patent implements preliminary action by providing dedicated retention control signals (CLK_POS_RET and CLK_NEG_RET) that are generated in advance and remain active during power collapse events. These signals ensure that retention flip-flops maintain their data storage capability before, during, and after power collapse, preventing operational data loss while enabling energy savings in non-critical circuit portions.
3Device complexity
If unified control scheme is implemented for positive-edge and negative-edge triggered flip-flops, then control complexity is reduced, but signal interference may occur
Solution Approach 1:
The patent applies segmentation by completely separating the control signal pathways for positive-edge and negative-edge triggered retention flip-flops. Each flip-flop type has its own dedicated clock input signals (CLK_POS and CLK_NEG) and retention control signals (CLK_POS_RET and CLK_NEG_RET), eliminating any possibility of signal interference while maintaining a relatively simple control architecture through modular signal distribution.
Data Source
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AI summary
An integrated circuit (IC) is disclosed having a unified control scheme and a unifying architecture for different types of retention flip-flops (RFFs). In an example aspect, an IC includes a constant power rail to provide power during a power collapse period and a collapsible power rail to cease providing power during the power collapse period. The IC also includes a positive-edge-triggered (PET) RFF and a negative-edge-triggered (NET) RFF. The PET RFF includes a master portion and a slave portion, with the slave portion coupled to the constant power rail and the master portion coupled to the collapsible power rail. The NET RFF includes master and slave portions, with the master portion coupled to the constant power rail and the slave portion coupled to the collapsible power rail. In another example aspect, a control signal based on a clock and a retention signal may be routed to both RFFs.