Retention Flip-Flop Power Gating Across Split Dies to Cut Leak Current
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Solution Overview
Problem
Conventional retention flip-flop circuits in semiconductor devices experience high leak current due to the use of two switches, which is exacerbated by miniaturization processes with small wiring widths, leading to increased current leakage.
Innovation Solution
The semiconductor device is configured with a first switch formed in a die with a large wiring width and a second switch formed in a die with a small wiring width, where the first switch is controlled to maintain power supply to a retention flip-flop circuit while the second switch is controlled to cut off power supply, thereby reducing overall leak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two switches are used in a retention flip-flop circuit to maintain power supply during sleep state, then the circuit can quickly recover from sleep state, but the leak current increases due to two switches being mounted in miniaturized die with small wiring width
Solution Approach 1:
The invention divides the retention flip-flop circuit into two separate dies: a first die containing the first switch and a second die containing the second switch and retention flip-flop. This segmentation allows the first switch to be manufactured with larger wiring width (reducing its leak current) while the second switch uses miniaturized process, effectively reducing total leak current while maintaining the dual-switch power retention function.
Solution Approach 2:
The invention applies different manufacturing processes to different parts of the system: the first switch uses a first manufacturing process optimized for large wiring width (minimizing leak current), while the second switch and retention flip-flop use a second miniaturization process. This local optimization of quality parameters resolves the contradiction between reliability and energy loss.
2Volume of moving object
If miniaturization process with small wiring width is used to reduce device size, then the semiconductor device can be more compact, but the leak current increases due to smaller wiring width
Solution Approach 1:
The invention segments the device into two separate dies with different manufacturing processes. The first die uses a process optimized for large wiring width (low leak current), while the second die uses miniaturization process (small device size). This segmentation allows the system to achieve compact size through the second die while maintaining low leak current through the first die's larger wiring.
Solution Approach 2:
Different regions of the system use different manufacturing qualities: the first switch region uses large wiring width for low leak current, while the second switch and flip-flop region uses miniaturization for compact size. This local quality differentiation resolves the contradiction between device size and leak current.
Data Source
AI summary
A semiconductor device is formed by first and second dies manufactured by processes with different wiring widths and includes: a first switch, outputting an input power voltage when set to ON, and stopping output when set to OFF; and a second switch, outputting, from a second voltage output terminal, the power voltage output to a second voltage input terminal when set to ON and stopping output when set OFF; and at least one retention flip-flop, provided with: a first power terminal, connected with the second voltage output terminal; and a second power terminal, connected with the first voltage output terminal, and maintaining data when the power voltage is supplied to the second power terminal and supply of the power voltage to the first power terminal is cut off. The first switch is formed in a first die, and the second switch and retention flip-flop are formed in a second die.