Retention Latch Circuit Decoupled From Clock Leakage in Sleep Mode
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Solution Overview
Problem
Power gating technologies face increased power consumption due to high leakage current in the clock circuit when the system is in sleep mode, as the clock circuit is designed for performance and not optimized for low power consumption.
Innovation Solution
A data retention circuit comprising a master latch circuit, a slave latch circuit, and a control circuit, where the master latch and clock circuit are in a power ON/OFF domain, and the slave latch and control circuit are in a retention domain, with the control circuit switching off power to the master latch in sleep mode and transmitting a power management signal to the slave latch, allowing the slave latch to preserve data without relying on the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock circuit is connected to power source in sleep mode to maintain clock signal level, then the slave latch can preserve data, but the leakage current increases and power consumption increases
Solution Approach 1:
The flip-flop is divided into master latch and slave latch, with the master latch in power ON/OFF domain and slave latch in retention domain. This segmentation allows the master latch to be powered off in sleep mode while the slave latch remains powered to preserve data, eliminating the need for the entire clock circuit to remain powered.
Solution Approach 2:
A control circuit is introduced as an intermediary between the clock circuit and the slave latch. The control circuit receives power management signals and selectively connects the clock signal to the slave latch only when needed (in normal mode), while allowing the slave latch to operate independently in sleep mode, thus mediating the power consumption issue.
2Productivity
If the clock circuit uses larger logic gates and multi-threshold voltage technology to meet timing requirements, then the performance is improved, but the leakage current generated by the clock circuit increases
Solution Approach 1:
The clock circuit's functional requirement is segmented from the data retention function. The master latch (in power ON/OFF domain) handles timing-critical operations with the performance-oriented clock circuit, while the slave latch (in retention domain) handles data preservation without requiring the high-performance clock signal, thus isolating the leakage current problem to only when absolutely necessary.
Solution Approach 2:
The clock signal is applied periodically rather than continuously to the slave latch. The control circuit enables clock signal transmission only during normal operation mode when timing performance is needed, and disables it during sleep mode when only data retention is required, reducing the average leakage current.
Data Source
AI summary
A data retention circuit is provided in the invention. The data retention circuit includes a master latch circuit, a slave latch circuit, and a control circuit. The control circuit is coupled to the master latch circuit and the slave latch circuit and receives a clock signal from a clock circuit and a power management signal from a power management unit (PMU). In a normal operation mode, the control circuit transmits the clock signal to the master latch circuit and the slave latch circuit. In sleep mode, power to the master latch circuit is switched off and the control circuit transmits the power management signal to the slave latch circuit.