Retention Latch Circuit for Low-Leakage State Hold
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Solution Overview
Problem
Conventional state retention circuits in semiconductor devices consume significant power due to always-on buffers during power reduction modes, as they maintain leakage current to retain the state of data storage elements, leading to increased energy consumption.
Innovation Solution
The implementation of a semiconductor device with a retention latch powered by a retention supply voltage, which toggles a retention node between states to hold the state of data storage elements during power reduction modes, and a buffer tree powered by the primary supply voltage that is completely powered down during this mode, reducing unnecessary power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If always on buffers (AOB) are used to route retention signals to storage latches during power reduction mode, then the state of data storage elements is retained, but leakage current flows continuously consuming significant power
Solution Approach 1:
The buffer tree is configured to be dynamically powered down during power reduction mode while retaining its signal routing capability. The retention signal path remains intact through the buffer tree structure, but power supply to the buffers is eliminated, making the system dynamic in its power consumption characteristics rather than static always-on operation
Solution Approach 2:
The harmful leakage current consumption is extracted and removed from the system by powering down the buffer tree during power reduction mode. The essential function of state retention is preserved through the retention latches and signal paths, while the energy-wasting buffer operation is taken out of the active state
2Use of energy by moving object
If the primary supply voltage is de-energized to power down circuitry during power reduction mode, then power consumption is reduced, but the state of data storage elements must be saved externally
Solution Approach 1:
The power supply system is segmented into two independent voltage domains: the primary supply voltage for normal circuit operation and the retention supply voltage for state preservation. This segmentation allows the retention circuitry to be independently powered and controlled, enabling selective powering down of different circuit portions without affecting state retention functionality
Solution Approach 2:
The retention supply voltage acts as an intermediary power source that bridges the gap between complete power down and full operation. It provides just enough power to the retention latches and buffer tree to maintain state information without requiring full circuit operation, serving as a mediator between power savings and state preservation needs
Data Source
AI summary
A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.