Retention Model Partitioning for RTL Verification Bottlenecks
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Solution Overview
Problem
The use of modified state retention cells in circuit designs leads to extremely long RTL processing times due to incompatibilities between conventional RTL and UPF retention model descriptions, causing performance and capacity issues, as well as challenges in flop/latch inferencing and simulation semantics differences, which existing technologies have failed to adequately address.
Innovation Solution
A retention model is partitioned into a sequential block and a retention controller block, with the sequential block configured to implement a selected retention strategy via signal path control signals, and entering a default operating mode to simulate a standard flip-flop or latch, thereby reducing RTL verification processing time and facilitating efficient logical equivalence checking between RTL and UPF descriptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If modified state retention cells are used to support UPF retention strategies, then retention functionality is improved, but RTL processing time increases extremely
Solution Approach 1:
The retention model is divided into two separate blocks: a sequential block that handles standard flip-flop/latch functionality and a retention controller block that manages retention strategies. This segmentation allows the sequential block to be processed efficiently by RTL simulators using standard Verilog always blocks, while the retention controller block handles UPF-specific retention logic separately, thus reducing overall RTL processing time while maintaining retention functionality.
Solution Approach 2:
A retention controller block is introduced as an intermediary between the sequential block and the UPF retention logic. This controller translates UPF retention strategies into control signals that configure the sequential block's signal routing circuit, enabling the sequential block to implement different retention strategies without requiring complex modifications to the core sequential logic processing.
2Adaptability or versatility
If retention controller block is added to implement retention strategies, then retention control capability is improved, but device complexity increases
Solution Approach 1:
The retention controller block is designed to handle multiple UPF retention strategies (e.g., power-down retention, idle retention, and no retention) through a unified control mechanism. The controller generates control signals that configure the sequential block's signal routing circuit to implement different retention behaviors, providing multi-functionality without requiring separate hardware structures for each strategy.
Solution Approach 2:
The signal routing circuit within the sequential block is made dynamically reconfigurable based on control signals from the retention controller. This dynamic configuration allows the same sequential block structure to adapt to different retention strategies by changing signal paths rather than requiring different hardware structures, thus managing complexity while maintaining versatility.
3Adaptability or versatility
If signal routing circuit is made reconfigurable to support multiple retention strategies, then strategy flexibility is improved, but processing speed decreases
Solution Approach 1:
The signal routing circuit is pre-configured with multiple fixed signal paths that can be selectively activated. Rather than dynamically creating new paths during operation, the circuit prepares all possible routing configurations in advance through its structural design, and the retention controller simply selects the appropriate pre-configured path by activating corresponding control signals, thus maintaining processing speed while supporting flexibility.
4Productivity
If retention model is partitioned into sequential block and retention controller, then RTL verification efficiency is improved, but model complexity increases
Solution Approach 1:
The sequential block is designed with local quality by separating concerns: it contains the essential sequential logic with a signal routing circuit that can be configured in different ways. The retention controller block handles the complexity of UPF strategy interpretation. This local quality differentiation allows RTL simulators to efficiently process the sequential block using standard Verilog semantics while the retention controller handles the complex UPF-specific logic separately.
Data Source
AI summary
A retention model includes a sequential block including two flip-flop/latch elements and a signal routing circuit having a network of alternative signal paths controlled by path control signals, which are generated by a retention controller block. The signal routing circuit enters a default operating mode when the signal path control signals are de-asserted, whereby the retention model implements a standard flip-flop/latch functionality in response to generic UPF signals applied to the model's generic input nodes, thereby facilitating RTL simulation of the retention model using a Verilog original always command. A selected retention strategy is implemented by modifying a retention controller block to assert a selected combination of path control signals, whereby the retention model may be implemented during UPF simulation using a map_retention_cell command. Restrictions prevent modification of the sequential block and path control signals and prevent use of generic input signals by the retention controller block.