Retention Reset Flip-Flop with Integrated Reset Logic for Low Power
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Solution Overview
Problem
Existing semiconductor devices with retention flip-flops face challenges in reducing size and power consumption, particularly due to the need for discrete circuits and logic that increase size and power consumption when implementing power gating techniques to reduce leakage current.
Innovation Solution
A semiconductor device design incorporating a master latch, slave latch, and logic gates that utilize local and global power supply voltages, along with a power gating circuit to selectively apply power, allowing the retention reset flip-flop to operate in normal and retention modes, minimizing power usage and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete circuits and logic are used to perform reset function on retention flip-flop, then the reset function is achieved, but the size of the flip-flop increases and power consumption increases
Solution Approach 1:
The reset function is merged into the flip-flop structure itself by integrating reset logic within the latch circuits. The reset signal is combined with clock and data signals through shared logic gates (AND/OR gates) that are already part of the flip-flop's data path, eliminating the need for separate discrete reset circuits.
Solution Approach 2:
The logic gates within the flip-flop are designed to perform multiple functions: they handle both data transmission and reset operations. The same gates that process clock and data signals also process reset signals, allowing a single circuit element to serve universal purposes for both data storage and reset functionality.
2Reliability
If discrete circuits and logic are used to perform reset function on retention flip-flop, then the reset function is achieved, but power consumption increases
Solution Approach 1:
The reset function is merged into the flip-flop structure itself by integrating reset logic within the latch circuits. The reset signal is combined with clock and data signals through shared logic gates (AND/OR gates) that are already part of the flip-flop's data path, eliminating the need for separate discrete reset circuits.
Solution Approach 2:
The logic gates within the flip-flop are designed to perform multiple functions: they handle both data transmission and reset operations. The same gates that process clock and data signals also process reset signals, allowing a single circuit element to serve universal purposes for both data storage and reset functionality.
3Use of energy by moving object
If power gating technique is used to reduce leakage current, then power consumption is reduced, but data in data storage flip-flop must be transferred to another location
Solution Approach 1:
The retention signal is activated before power gating occurs to ensure data is safely stored in the retention flip-flop. This preliminary action of setting the retention signal prepares the circuit for power gating by ensuring data is in a stable state that can withstand the power transition.
Solution Approach 2:
The retention signal acts as an intermediary that bridges the data storage function and the power gating control. It mediates between the need to maintain data integrity and the need to gate power for leakage reduction, allowing smooth transition between active and low-power states without requiring data transfer.
4Use of energy by moving object
If local and global power supply voltages are used, then power consumption is reduced in retention mode, but circuit complexity increases
Solution Approach 1:
Different parts of the circuit are supplied with different power voltages according to their functional requirements. The master latch uses local power voltage (VDD) for high-speed operation, while the slave latch uses global power voltage (VDDA) for low-power retention, optimizing each section's performance characteristics.
Solution Approach 2:
The power supply network is segmented into local and global voltage domains. The flip-flop is divided into sections that can be independently powered, allowing selective activation of circuit blocks based on operational mode, thereby reducing overall power consumption while maintaining necessary functionality.
Data Source
AI summary
A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.