Retention Voltage Generator Circuit Using Dummy Cell Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for generating a retention voltage level in computer systems lack flexibility and efficiency, as they provide a fixed voltage level for retention mode, failing to account for variations in electrical characteristics of memory cells due to manufacturing processes, and consume more power than they save.
Innovation Solution
A power converter circuit that adjusts the retention voltage level using the leakage current of dummy memory cells, generating a retention voltage level on an array power supply node and optionally generating a clock signal, allowing for adaptive voltage adjustment based on electrical characteristics and manufacturing variations while maintaining low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed voltage level is provided for retention mode, then power consumption is reduced, but flexibility and efficiency are lost due to inability to account for manufacturing variations
Solution Approach 1:
The power converter circuit automatically adjusts the retention voltage level by utilizing leakage current from dummy memory cells as feedback. This self-regulating mechanism eliminates the need for external control circuits or manual adjustment, achieving adaptability without proportionally increasing system complexity
Solution Approach 2:
The circuit uses leakage current from dummy memory cells as a feedback signal to dynamically adjust the retention voltage level. This feedback mechanism enables the system to automatically compensate for manufacturing variations and electrical characteristic changes, providing flexibility while maintaining manageable complexity through a closed-loop control approach
2Use of energy by moving object
If a fixed voltage level is provided for retention mode, then device complexity is reduced, but power consumption increases due to inability to optimize for actual memory cell characteristics
Solution Approach 1:
The power converter circuit autonomously optimizes power consumption by using leakage current from dummy memory cells to automatically adjust retention voltage. This self-service approach achieves power optimization without requiring complex external power management infrastructure
Solution Approach 2:
The circuit dynamically changes the retention voltage parameter based on actual memory cell characteristics and leakage current measurements. This parameter adjustment enables optimal power consumption by matching voltage levels to actual device requirements rather than using fixed conservative values
3Productivity
If retention voltage level is adjusted using leakage current, then efficiency and flexibility are improved, but device complexity increases
Solution Approach 1:
The dummy memory cells serve dual purposes: they act as regular memory cells during normal operation and as sensors for leakage current measurement during retention mode. This multi-functionality enables efficient voltage adjustment without requiring separate dedicated sensing structures, thereby limiting complexity increase
Solution Approach 2:
The power converter circuit combines the voltage adjustment functionality with the existing memory cell structure by using leakage current from dummy cells. This merging of functions achieves efficiency improvements while avoiding the complexity of completely separate control systems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a flexible and efficient retention voltage level that tracks changes in memory cell characteristics, ensuring data retention with reduced power consumption, thereby enhancing the power management efficiency in computer systems.
Implementation Method 1
adjust the retention voltage level on an array power supply node using a leakage current of a plurality of dummy memory cells
Data Source
AI summary
Memory circuits used in computer systems may have different operating modes. In a retention mode, a voltage level of an array power supply node coupled to memory cells included in the memory circuit is reduced to a level sufficient to retain data, but not to perform read and write operations to the memory cells. A power converter circuit may be configured to generate the retention voltage level, and adjust the retention voltage level using a leakage current of dummy memory cells included in the memory circuit.