Logical to Physical Mapping via Reticle Fault Patterns
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Solution Overview
Problem
The complexity of reticles used in integrated circuit fabrication leads to errors and delays in production due to the difficulty in physically locating faulty components on densely packed dies, as conventional methods are not feasible for complex dies with billions of components.
Innovation Solution
A method involving the fabrication of a reticle with a known fault pattern, which causes specific components on the die to be faulty, allowing for the mapping of logical addresses to physical locations by correlating the fault pattern's shape and orientation, thereby facilitating the identification of defective components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional physical location methods are used to locate faulty components on densely packed dies, then component location can be achieved, but the time required becomes extremely long (hundreds of man hours)
Solution Approach 1:
The patent introduces a known fault pattern during reticle fabrication before die production. This preliminary action creates a reference map that correlates logical addresses to physical locations. When a die is tested and faults are detected, the pre-established fault pattern allows immediate identification of physical component locations without time-consuming manual searching, thus resolving the time loss while maintaining location accuracy
Solution Approach 2:
The patent creates a copy of the fault pattern at known physical locations on the reticle. This copy serves as a reference that can be correlated with test results from actual dies. By comparing the detected fault pattern on a die with the known fault pattern on the reticle, the system可以快速 determine physical component locations corresponding to logical addresses, eliminating the need for manual physical location methods
2Quantity of substance
If reticles are made with extremely high density to accommodate billions of components, then circuit functionality is achieved, but errors in the reticle and mapping documentation become more likely
Solution Approach 1:
The patent implements a feedback mechanism where a known fault pattern is intentionally introduced during reticle fabrication. This creates a controlled reference that can be used to verify the accuracy of the logical to physical mapping. By comparing actual die test results against the known fault pattern, errors in reticle fabrication or mapping documentation can be detected and corrected, thereby improving reliability while maintaining high component density
Solution Approach 2:
The known fault pattern is established as a preliminary reference during reticle fabrication. This preliminary action creates a verification mechanism that can identify mapping errors before production dies are manufactured. By having this reference in place beforehand, the system can detect and correct reticle errors, reducing the overall error rate despite high component density
3Measurement precision
If laser induced defects are used to confirm logical to physical mapping, then mapping accuracy can be verified, but the method is not feasible for complex dies with billions of components
Solution Approach 1:
The patent creates a copy of the fault pattern at known physical locations on the reticle during fabrication. This copy serves as a reference map that correlates logical addresses to physical locations. When dies are tested, the detected fault pattern can be directly compared to this reference copy, enabling verification of logical to physical mapping without requiring laser induced defects or manual physical location methods, thus making the verification feasible for complex high-density dies
Solution Approach 2:
The patent extracts the verification function from complex physical methods (laser induced defects, manual location) and replaces it with a pattern comparison approach. By separating the known fault pattern creation from the verification process, the system can verify mapping accuracy through simple pattern matching rather than complex physical intervention, making the method scalable to dies with billions of components
Data Source
AI summary
Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.