Reticle Field Extension Zone for IC Dimension Expansion
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Solution Overview
Problem
In semiconductor manufacturing, the limited size of the exposure field of the illumination tool restricts the surface area that can be patterned in a single exposure, limiting the dimension of integrated circuits (ICs) formed on wafers with reticle fields.
Innovation Solution
The method involves defining an extension zone outside a first area and a forbidden zone inside a second area on adjacent reticle fields, allowing a second layout shape on a second design level to overlap and form connections with the first layout shape, effectively increasing the IC dimension beyond the exposure field size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the exposure field size is limited, then the manufacturing process remains manageable, but the IC size cannot be increased
Solution Approach 1:
The IC layout is divided into multiple reticle fields that can be processed separately through repeated exposure steps. Each reticle field contains a portion of the overall IC design, allowing the large IC to be manufactured by assembling multiple smaller patterned regions. This segmentation enables the IC size to exceed the exposure field limitations while maintaining manageable processing steps.
Solution Approach 2:
Multiple reticle fields are arranged in a grid pattern on the wafer, with each field containing circuitry that will eventually form part of the larger IC. The reticle fields are nested within the wafer surface, allowing sequential exposure and processing of multiple fields that collectively form the complete IC design beyond the single exposure field size.
2Manufacturing precision
If reticle fields are processed separately, then exposure precision is maintained, but connections between adjacent fields become difficult
Solution Approach 1:
Connection structures are pre-designed and positioned at the boundaries of reticle fields during the layout phase. These pre-planned connection regions include features such as alignment marks, contact pads, and interconnect structures that are specifically configured to facilitate joining between adjacent fields. This preliminary preparation simplifies the subsequent connection formation process while maintaining exposure precision.
Solution Approach 2:
Connection structures act as intermediary elements between adjacent reticle fields. These intermediaries include boundary features, alignment markers, and interconnect structures that mediate the joining process between separately processed fields. The intermediary structures enable precise alignment and electrical connections between fields without requiring the entire IC to be exposed in a single step.
3Adaptability or versatility
If the IC size is doubled by using adjacent reticle fields, then functionality is improved, but the forbidden zone constraints complicate the layout
Solution Approach 1:
The layout design applies different characteristics to different regions of the reticle fields. Extension zones are created at the boundaries where connection to adjacent fields is needed, while the main IC area maintains standard design rules. This local differentiation allows connection features to be optimized for inter-field joining while the rest of the layout maintains optimal IC design characteristics, managing complexity through localized adaptations.
Solution Approach 2:
The layout utilizes vertical stacking of design levels to manage the forbidden zone constraints. By placing connection structures at different vertical levels (different design layers), the layout can route signals and form connections between reticle fields without requiring additional horizontal space. This dimensional approach allows the IC to be doubled in functionality while managing layout complexity through vertical arrangement of connection structures.
Data Source
AI summary
One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.