Reticle Enhancement Mask Modeling Without Tile Stitching Errors
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Solution Overview
Problem
Conventional reticle enhancement technologies face challenges in efficiently optimizing lithographic masks for submicron manufacturing, particularly in handling large designs and managing stitching errors in tile-based computing, which affects yield and resilience to manufacturing variation.
Innovation Solution
The method involves creating a Continuous Tone Mask (CTM) and converting it to a Quantized Tone Mask (QTM) for large design areas, using iterative optimization and distributed computing to update halos concurrently, avoiding stitching issues by optimizing tiles with extended halo regions on separate computing nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional tile-based computing is used for optimizing large mask layers, then computational efficiency is improved, but stitching errors occur at tile boundaries affecting yield
Solution Approach 1:
The patent divides the large mask layer into multiple smaller tiles that can be processed independently and in parallel. Each tile is optimized separately through iterative refinement, allowing computational efficiency while maintaining overall pattern integrity by managing boundary conditions between tiles
Solution Approach 2:
The patent introduces a halo region around each tile that acts as an intermediary buffer zone. This halo contains preview patterns from adjacent tiles, allowing the optimization algorithm to account for boundary effects and stitching conditions without requiring complex inter-tile coordination, thus preventing stitching errors while maintaining parallel processing capability
2Manufacturing precision
If iterative optimization is applied to entire large designs, then pattern accuracy is improved, but computational time and resources increase significantly
Solution Approach 1:
The design is segmented into multiple independent tiles that can be optimized in parallel rather than as a single large unit. This reduces the computational complexity from O(N²) to approximately O(N), where N is the number of tiles, significantly reducing computational time while maintaining pattern accuracy through iterative optimization of each tile
Solution Approach 2:
The patent applies iterative optimization to each tile individually rather than to the entire design at once. This partial action approach allows the system to achieve sufficient pattern accuracy for each tile independently, avoiding the excessive computational burden of global optimization while still producing high-quality results through localized refinement
3Reliability
If mask optimization accounts for manufacturing variation, then yield and resilience are improved, but device complexity and computational overhead increase
Solution Approach 1:
The patent incorporates manufacturing variation effects into the tile optimization process in advance, before actual mask fabrication. By pre-computing compensation patterns that account for expected manufacturing variations, the system improves yield and resilience without adding complexity to the physical manufacturing process itself
Solution Approach 2:
The optimization algorithm automatically adjusts tile patterns to compensate for manufacturing variations through self-correction mechanisms. The iterative optimization process inherently accounts for variation by refining patterns until they meet specified tolerance criteria, eliminating the need for external complexity management or post-fabrication adjustments
Data Source
AI summary
A method for manufacturing a semiconductor chip involves generating exposure instructions from a Quantized Tone Mask (QTM) using charged particle beam technology, wherein the QTM is a 2-tone mask translated from a Continuous Tone Mask (CTM) using a cost function for mask value regularization.