Reticle-Stitched Base Die Layout for Low-Overhead Stacked Interconnects
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Solution Overview
Problem
The increasing bandwidth requirements in processor complexes are not adequately met by existing die-to-die communication methods such as C4 bumps and EMIBs, limiting the performance of advanced compute systems.
Innovation Solution
Implementing reticle stitching techniques to fabricate a single monolithic base die with selectively patterned through silicon vias and metallization layers, allowing for high-bandwidth communication between regions of the die using reticle stitched metal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If C4 bumps are used for die-to-die communication, then the communication between dies is established, but the bandwidth is very poor
Solution Approach 1:
The patent introduces an intermediate structure (the monolithic base die with through-silicon vias and stacked dies) to mediate the communication between separate dies. This intermediary enables high-bandwidth communication pathways that overcome the limitations of direct C4 bump connections, achieving up to 3x bandwidth improvement while maintaining reliable die-to-die communication.
2Productivity
If EMIBs are used to improve bandwidth, then the bandwidth between dies is improved, but the solution cannot provide necessary bandwidth as the number of execution units increases
Solution Approach 1:
The patent segments the communication pathway into multiple components: the monolithic base die, through-silicon vias, and stacked dies. This segmentation allows for scalable bandwidth by adding more stacked dies or increasing the number of through-silicon vias, enabling the system to adapt to increasing numbers of execution units and maintain necessary bandwidth.
Solution Approach 2:
The patent transitions from two-dimensional die-to-die communication (EMIBs) to three-dimensional stacked die communication through through-silicon vias. This dimensional change enables vertical communication pathways that provide scalable bandwidth capacity to support increasing numbers of execution units and nodes in the processor complex.
3Productivity
If reticle stitching is used to fabricate monolithic base die, then high-bandwidth communication is achieved, but the area overhead of reticle stitching increases
Solution Approach 1:
The patent merges multiple fabrication processes and structures into a unified monolithic base die using reticle stitching. By combining through-silicon via formation, metallization layers, and stacked die integration into a single monolithic structure, the design achieves high bandwidth communication while optimizing area usage through shared resources and integrated pathways.
Data Source
AI summary
Compute complexes, base dies, and methods related to leveraging reticle stitching for improved device interconnects are discussed. A base die includes first and second regions having device layers, lower level metallization layers, and through vias fabricated using the same reticles. In the first region, a first subset of the through vias are contacted by higher metallization layers and, in the second region, a second distinct subset of the through vias are contacted by higher metallization layers such that the first and second metallization layers provide unique routing through vias having shared layouts and relative locations in the first and second regions.