Reticle-Stitched IC Package Architecture With Photonic Interconnects

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Solution Overview

Problem

Current semiconductor manufacturing processes are limited by the size of reticles, which restrict the fabrication of large IC dies, and existing packaging architectures face bandwidth limitations due to interconnects in bridge dies, particularly in multi-chip packages.

Innovation Solution

Implement a microelectronic assembly with reticle stitching and photonic ICs to create a scalable package architecture, where IC dies are stacked vertically with conductive pathways in scribe regions and connected using photonic interconnects for enhanced bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If reticle stitching is used to fabricate larger IC dies, then the die size can exceed reticle limitations, but the manufacturing complexity increases

Engineering Contradiction:
ImproveIC die areaVSAvoidmanufacturing complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The manufacturing process is segmented into multiple stages: fabricating smaller dies within reticle size limits, then assembling them into larger die arrays through scribe region coupling. This segmentation allows each fabrication step to remain within standard reticle capabilities while achieving overall larger die areas through systematic assembly of multiple units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple smaller dies are nested or coupled together within a larger package structure, forming a hierarchical arrangement where individual dies are integrated into arrays. This nesting approach enables the system to achieve functionality equivalent to large dies while maintaining manufacturing simplicity through standardized smaller-unit fabrication.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If traditional electrical interconnects are used in bridge dies, then multi-chip packages can be assembled, but bandwidth is limited due to interconnect distances

Engineering Contradiction:
Improvedata transfer bandwidthVSAvoidinterconnect distance
Core Design Contradiction:
Quantity of substanceVSLength of stationary object

Solution Approach 1:

Traditional electrical interconnect systems are replaced with photonic interconnect systems using optical waveguides. This substitution transitions from electrical signal transmission through conductive pathways to optical signal transmission through photonic channels, enabling higher bandwidth and reduced signal interference while maintaining compact interconnect distances.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The fundamental transmission parameter is changed from electrical signals to optical signals. This parameter change enables simultaneous transmission of multiple wavelengths (WDM), dramatically increasing bandwidth capacity without proportionally increasing interconnect distance or physical footprint.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12543594B2Scalable package architecture using reticle stitching and photonics for integrated circuits
Publication Date: 2026.02.03 INTEL CORP
  • US12543594B2 patent drawing
  • US12543594B2 patent drawing
  • US12543594B2 patent drawing

AI summary

Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die including a plurality of first circuits separated by scribe regions, and a plurality of second IC dies coupled to the first IC die, each one of the second IC dies being coupled proximate and adjacent to a corresponding one of the first circuits and conductively coupled to the corresponding one of the first circuits. One or more of the second IC dies comprises a second circuit different from the first circuit, adjacent ones of the first circuits are coupled by a conductive pathway through the corresponding scribe regions, and the first IC die and the second IC die are coupled by interconnects having a pitch not more than 10 micrometers between adjacent interconnects.