Retime Word Circuit for Phase-Coherent Bus Clock Crossing
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Solution Overview
Problem
Fractional-N phase-locked loops (PLLs) face issues with phase coherency when tuning away from and returning to a frequency, leading to random phase relationships between the output and reference signals, which can break phase coherence and cause synchronization failures in asynchronous clock domains.
Innovation Solution
A retime word circuit is implemented to synchronize the reference clock with the divided clock in a phase coherent delta-sigma modulator PLL, ensuring the divide word changes only at the end of a divide cycle, using two register banks and a D-type flip-flop to manage edge triggering and meta-stability, and a high-gain buffer to resolve ambiguity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the DSM is clocked off the divided waveform to enable fractional reference frequency tuning, then frequency tuning capability is improved, but phase coherence is lost when tuning away and returning to a frequency
Solution Approach 1:
A retiming circuit is introduced as an intermediary between the DSM and the divide-by-N integer divider. This circuit includes a positive-edge triggered capture register, a negative-edge triggered capture register, and a selection circuit that samples the state of the reference clock and a second asynchronous clock to select which register's output is passed to the divider. This intermediary ensures that the divide word changes only at the appropriate clock edge, maintaining phase coherence while allowing the DSM to be clocked off the divided waveform for frequency tuning.
2Adaptability or versatility
If the divide word changes at any time during the divide cycle, then frequency tuning flexibility is improved, but synchronization failures occur due to incorrect timing
Solution Approach 1:
The retiming circuit performs preliminary action by capturing the divide word in advance in two separate registers (positive-edge and negative-edge triggered) before it is needed by the divider. The selection circuit then determines which captured value should be passed to the divider based on the current clock state. This ensures that the divide word is always ready and correctly timed when needed, preventing synchronization failures while maintaining tuning flexibility.
3Adaptability or versatility
If the PLL returns to a previously generated frequency after tuning away, then frequency coverage is improved, but phase coherence is broken and random phase relationships occur
Solution Approach 1:
The retiming circuit provides feedback by continuously monitoring the state of both the reference clock and the second asynchronous clock, and using this information to select the appropriate register output. This feedback mechanism ensures that the divide word is updated at the correct moment, maintaining the phase relationship between the reference signal and the output signal even when the PLL tunes away and returns to a previously generated frequency.
Data Source
AI summary
Techniques are disclosed for managing the timing between two asynchronous clocks. The techniques are particularly well-suited for synchronizing the reference clock with the divided clock in a phase coherent DSM PLL application, but can be more broadly applied to any application that includes a need for synchronizing a data bus across a clock boundary. In one example embodiment, the techniques are implemented in a retime word circuit operatively coupled between a DSM and the divide-by-N integer divider of a PLL application. The retime word circuit receives the divide word from the DSM and generates a retimed divide word that can be applied to the divider. The retime word circuit maintains the reference clock frequency throughput, and forces the divide word seen by the divider to change only at end of a given divide cycle.