Retimed Circuit Structural Verification via Label Reverse Engineering
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Solution Overview
Problem
Current methods for verifying structural correctness and initial state equivalence in retimed circuits are inefficient, particularly in complex systems like FPGAs and ASICs, where formal verification is computationally difficult and time-consuming, and existing techniques do not effectively ensure the equivalence of flip-flops before and after retiming.
Innovation Solution
A method and apparatus that reverse-engineer the retimed circuit to verify structural correctness by solving for retiming labels, identifying unchanged and changed flip-flops, and using bounded sequential logic simulation to compare initial states, ensuring the retimed circuit's structural and functional equivalence to the original design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If formal verification is used to verify structural correctness and initial state equivalence in retimed circuits, then verification accuracy is improved, but verification time and computational resources increase significantly
Solution Approach 1:
The verification process is segmented into three distinct phases: (1) structural correctness verification by solving retiming labels to determine if the retimed circuit can be retimed back to the original, (2) initial state equivalence verification for unchanged flip-flops using retiming labels and weights, and (3) initial state equivalence verification for changed flip-flops using bounded sequential logic simulation. This segmentation allows each phase to use optimized methods appropriate to its specific verification goals, reducing overall computational burden while maintaining accuracy.
Solution Approach 2:
Instead of performing exhaustive formal verification on the entire retimed circuit, the patent applies partial verification actions: using retiming labels to verify structural correctness without full formal equivalence checking, using bounded sequential logic simulation with a limited number of time frames (determined by the maximum absolute value of retiming labels) instead of unlimited simulation, and focusing verification on specific flip-flop categories (unchanged vs. changed) with different methods.
2Reliability
If exhaustive formal verification is performed on all flip-flops in retimed circuits, then verification completeness is improved, but device complexity and computational difficulty increase
Solution Approach 1:
Flip-flops are segmented into two categories: unchanged flip-flops and changed flip-flops. Unchanged flip-flops are verified using a simplified method comparing initial states before and after retiming using retiming labels and weights. Changed flip-flops are verified using bounded sequential logic simulation. This segmentation reduces computational complexity by applying different verification strategies to different subsets of flip-flops while maintaining overall verification completeness.
Solution Approach 2:
Different verification methods with appropriate complexity levels are applied to different types of flip-flops based on their local characteristics. Unchanged flip-flops use a simpler verification approach, while changed flip-flops use a more rigorous bounded simulation approach. This local quality principle ensures verification completeness without uniformly applying high computational complexity to all flip-flops.
3Manufacturing precision
If retiming verification is performed on complex systems like FPGAs and ASICs with millions of gates, then design correctness is ensured, but verification resources and time consumption increase
Solution Approach 1:
The patent applies partial verification actions suitable for large-scale systems: using retiming labels to verify structural correctness without full formal equivalence checking of all circuits, using bounded sequential logic simulation with a limited number of time frames (determined by the maximum absolute value of retiming labels) instead of exhaustive simulation, and focusing verification on specific flip-flop categories. This approach ensures design correctness for complex systems while maintaining productivity by avoiding unnecessarily exhaustive verification.
4Ease of operation
If conventional verification methods are used without reverse engineering the retimed circuit, then verification simplicity is maintained, but verification accuracy and reliability decrease
Solution Approach 1:
The patent performs preliminary reverse engineering of the retimed circuit by solving for retiming labels before conducting the main verification tasks. This preliminary action determines how flip-flops were repositioned and identifies unchanged versus changed flip-flops, which enables subsequent verification steps to be performed more accurately and reliably while maintaining operational simplicity through automated processes.
Solution Approach 2:
Retiming labels serve as an intermediary data structure that captures the transformation from original to retimed circuit. By computing retiming labels first, the patent creates a mediator that enables accurate verification of structural correctness and initial state equivalence without requiring direct complex comparison of the entire retimed circuit, thus maintaining simplicity while improving reliability.
Data Source
AI summary
A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design.