Retimed Circuit Reset Sequence Adjustment
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Solution Overview
Problem
After register retiming in integrated circuits, the original reset sequence may not be effective for the retimed flip-flops, leading to unknown initial states during power-up, which can hinder proper reset and operation.
Innovation Solution
The proposed solution involves using CAD tools to generate an adjusted reset sequence by tracking register movements across different circuit elements, calculating an adjustment value, and prepending an adjustment sequence with arbitrary primary input values to delay the original reset sequence, ensuring the registers can be properly reset in the retimed circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If register retiming is performed to improve circuit performance, then clock frequency and performance increase, but the original reset sequence becomes ineffective and registers cannot be properly reset
Solution Approach 1:
The patent calculates the adjustment value before generating the reset sequence by analyzing register movements during retiming. This preliminary calculation determines how many clock cycles the reset sequence must be delayed to account for registers moved across combinational logic, ensuring the reset sequence is properly synchronized with the retimed circuit structure before reset operation occurs.
Solution Approach 2:
The patent modifies the reset sequence by changing its timing parameter - specifically, delaying the reset sequence by a calculated number of clock cycles (adjustment value). This parameter change transforms the original reset sequence into a modified version that accounts for register retiming, allowing the reset functionality to work correctly with the retimed circuit while maintaining the performance benefits of retiming.
2Productivity
If registers are moved across combinational logic during retiming, then delay distribution is balanced and performance increases, but tracking and calculating reset sequence adjustments becomes more complex
Solution Approach 1:
The patent divides the circuit into segments separated by non-justifiable elements (such as fan-out nodes). By segmenting the circuit at these boundary points, the patent can independently calculate adjustment values for each segment and combine them systematically. This segmentation approach breaks down the complex task of tracking all register movements into manageable segments, reducing the overall calculation complexity while maintaining accuracy.
Solution Approach 2:
The patent introduces non-justifiable elements as intermediary markers to track register movements. These elements serve as reference points that facilitate the calculation of adjustment values by providing clear boundaries for analyzing register retiming. The intermediaries simplify the tracking process by creating discrete segments that can be analyzed independently, making the overall calculation more systematic and less complex.
Data Source
AI summary
Integrated circuit design computing equipment may perform register moves within a circuit design. When moving the registers, counter values may be maintained for non-justifiable elements. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that is used to generate a sequence for resetting the circuit design. The adjustment value may be bound by a user-specified maximum value. The user-specified maximum value may constrain logic/physical synthesis transforms and local/global retiming operations. If the counter value for a non-justifiable element is equal to the user-specified maximum value, then all future forward retiming across that element is prevented. If the maximum counter value is less than the user-specified maximum value, the user may optionally shorten the reset sequence.