Retimed Circuit Initial State Equivalence Verification
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Solution Overview
Problem
In the design of systems on target devices like FPGAs and ASICs, verifying the structural correctness and initial state equivalence of retimed circuits is challenging due to the complexity of retiming processes, which often requires computationally intensive formal verification methods and may not effectively identify changes in flip-flop positions and initial states.
Innovation Solution
A method and apparatus that reverse-engineer the original circuit to verify structural correctness by solving for retiming labels, identify unchanged and changed flip-flops, and perform bounded sequential logic simulation to ensure initial state equivalence, using retiming labels to compare signal values across time frames in retimed circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification methods are used to verify structural correctness of retimed circuits, then verification thoroughness is improved, but computational complexity increases
Solution Approach 1:
The verification process is segmented into three distinct phases: structural correctness verification (separate from functional verification), initial state equivalence verification for unchanged flip-flops, and initial state equivalence verification for changed flip-flops. This segmentation allows each aspect to be verified independently with appropriate methods, reducing overall computational complexity while maintaining thoroughness.
Solution Approach 2:
Retiming labels are introduced as an intermediary concept to track and verify flip-flop repositioning. These labels serve as a mediator between the original circuit and retimed circuit, enabling structural correctness verification without requiring complete formal equivalence checking of the entire circuit.
2Reliability
If comprehensive formal verification is performed on retimed circuits, then functional correctness is ensured, but verification time increases
Solution Approach 1:
Verification time is reduced by segmenting the verification process into targeted components: structural correctness (using retiming labels), unchanged flip-flop initial states (using weight comparisons), and changed flip-flop initial states (using bounded sequential simulation). This avoids the need for time-consuming complete formal verification while ensuring functional correctness.
Solution Approach 2:
Instead of performing exhaustive formal verification on all circuit elements, the method applies partial verification focused on critical aspects: structural correctness via retiming labels and initial state equivalence via bounded simulation. This partial action approach achieves sufficient verification without excessive time investment.
3Difficulty of detecting and measuring
If traditional verification methods are used to identify flip-flop position changes, then detection capability is maintained, but detection precision decreases
Solution Approach 1:
Retiming labels serve as precise intermediaries to track flip-flop positions. Each flip-flop is assigned a label indicating its position change, enabling precise detection and measurement of position changes without the ambiguity of traditional verification methods that treat all circuit elements uniformly.
Solution Approach 2:
The verification approach changes from detecting structural differences to measuring parameter changes, specifically the retiming label values that quantify flip-flop position changes. This parameter-based measurement provides precise detection of position changes while maintaining the capability to handle complex retiming transformations.
Data Source
AI summary
A method for designing a system on a target device includes performing register retiming on an original design to generate a retimed design of the system. Compare points are identified in the original design and the retimed design. Equality constraints are defined for all compare points. Starting from the initial states of the original and retimed circuits, bounded sequential logic simulation is performed for a maximum number of time frames determined as the maximum absolute value of retiming variables computed during structural verification. Whether changed flip-flops in the retimed design have initial states that are correct are determined by comparing signal values at the compare points from the bounded sequential logic simulation.