Re-Timed Clock Generation Circuit for Low Phase Noise
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Solution Overview
Problem
Existing clock generation circuits in wireless communication networks face challenges with phase noise and power consumption, particularly due to the contribution of frequency divider circuitry, which affects the stability and efficiency of local oscillator signals used in mixers for upconversion and downconversion processes.
Innovation Solution
A clock generation circuit is designed with cascode-connected transistors and a frequency divider, where the input clock signal is applied to the gates of the transistors, and the frequency-divided signal is provided to the source of one transistor, generating an output clock signal at the drains, thereby reducing phase noise and power consumption by re-timing the signal and eliminating the phase noise contribution from the frequency divider.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If frequency divider circuitry is used to generate clock signals, then clock signal generation is achieved, but phase noise performance deteriorates
Solution Approach 1:
The patent extracts the frequency divider circuit from the critical clock signal path. The retiming circuit takes the divided clock signal and regenerates it through clean switching transistors, effectively removing the phase noise contribution of the frequency divider from the output clock signal while maintaining the divided frequency functionality.
Solution Approach 2:
The retiming circuit acts as an intermediary between the frequency divider and the rest of the system. It receives the noisy divided clock signal, regenerates it through clean transistor switching, and outputs a low-phase-noise clock signal, mediating the conflict between frequency division and phase noise performance.
2Power
If frequency divider circuitry is used to generate clock signals, then clock signal generation is achieved, but power consumption increases
Solution Approach 1:
The patent extracts only the essential frequency division functionality from the traditional clock generation approach. By using a simple retiming circuit with transistors instead of a complex frequency divider, it achieves frequency division with significantly reduced power consumption while maintaining clock signal stability.
3Measurement precision
If frequency divider circuitry is used, then frequency division is achieved, but residual sideband statistics deteriorate
Solution Approach 1:
The patent extracts the core frequency division function and implements it through a simple retiming circuit rather than a complex frequency divider. This eliminates the sources of mismatch and distortion in traditional frequency dividers, significantly improving residual sideband statistics.
Solution Approach 2:
The patent changes the operational parameters of the clock generation circuit by using clean transistor switching in the retiming circuit rather than complex digital logic. This parameter change eliminates the mismatch and distortion that degrade residual sideband statistics in traditional frequency dividers.
Data Source
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AI summary
Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.