Dividerless Fractional Analog PLL for Low-Power Frequency Locking
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Solution Overview
Problem
Phase lock loops (PLLs) in wireless devices consume significant power, especially in sleep or listen modes, due to the power requirements of feedback divider circuits, which limits battery life and performance in high-frequency wireless communications.
Innovation Solution
An integrated circuit with a fractional PLL configured to run in a divider disabled mode, using a re-timed clock signal and sigma-delta modulation to adjust the VCO output without the feedback divider, reducing power consumption and improving residual frequency error and phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the feedback divider circuit is enabled in a fractional PLL, then accurate frequency locking is achieved, but power consumption increases significantly
Solution Approach 1:
The patent extracts and removes the feedback divider circuit from the PLL system during low-power modes. By taking out this specific component that consumes significant power, the system achieves substantial power reduction while maintaining acceptable frequency locking through alternative mechanisms such as open-loop VCO operation or simplified feedback paths.
Solution Approach 2:
The system dynamically adjusts the PLL configuration based on operational requirements. During high-performance modes, the full PLL with feedback divider is activated for accurate frequency locking. During low-power modes, the system transitions to a simplified configuration without the feedback divider, enabling adaptive power management that balances performance and energy consumption.
2Use of energy by moving object
If the VCO runs in open-loop mode to disable the feedback divider, then power consumption is reduced, but residual frequency error and phase noise increase
Solution Approach 1:
Instead of completely disabling frequency control, the system applies partial feedback action through alternative paths or reduced-precision mechanisms. This allows the VCO to operate in a semi-closed loop mode during low-power operation, providing enough frequency accuracy to meet requirements while consuming significantly less power than full closed-loop operation.
3Use of energy by moving object
If the feedback divider is disabled during listen or sniff mode, then power consumption is reduced, but the ability to maintain accurate LO frequency is compromised
Solution Approach 1:
The system creates a simplified copy of the feedback control mechanism that operates during low-power modes. This copy provides essential frequency stabilization without the full complexity and power consumption of the original feedback divider circuit, maintaining sufficient frequency stability for listen or sniff operations.
Data Source
AI summary
An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal.