Low-Latency Retimer Clock Engine for Seamless Source Switchover
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Solution Overview
Problem
Conventional retimer architectures incur significant latency due to domain crossing between receive and local clocks, which disrupts seamless clock switchover and affects the reliability of high-speed signaling over long distances.
Innovation Solution
A seamless-clock-switchover (SCS) retimer system that alternately selects between receive and local clock sources, ensuring seamless switchover without disrupting the core clock period or duty cycle, by aligning and switching between clock sources within the clock engine, and distributing the local clock throughout the retimer architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional retimer architectures use domain crossing between receive and local clocks, then clock sources can be independently managed, but latency increases significantly
Solution Approach 1:
The patent merges the receive clock and local clock into a single unified clock domain by seamlessly switching between clock sources without transitioning between domains. The clock engine selectively applies either the receive clock or local clock to the retimer circuitry, eliminating the need for complex domain crossing mechanisms and reducing latency associated with buffer-based domain transitions.
Solution Approach 2:
The patent introduces a clock engine as an intermediary component that manages clock source selection. This clock engine receives both the receive clock and local clock inputs and selectively outputs one of them to the retimer circuitry, acting as a mediator that avoids direct domain crossing while maintaining independent clock source management.
2Loss of time
If seamless clock switchover is implemented, then latency is reduced, but clock alignment precision requirements increase
Solution Approach 1:
The patent implements preliminary action by performing clock alignment preparation in advance. The system continuously monitors and prepares for clock source transitions by pre-synchronizing the receive clock and local clock phases before actual switchover occurs. This preliminary synchronization ensures that when switching happens, the transition is seamless without disrupting the clock domain, thereby reducing latency while meeting precision requirements.
3Loss of time
If receive clock is used throughout the symbol progression path, then latency is minimized, but reliability decreases when traffic is absent
Solution Approach 1:
The patent applies dynamics by making the clock source selection adaptive rather than static. The system dynamically switches between using the receive clock (when traffic is present to minimize latency) and the local clock (when traffic is absent to ensure reliability). The clock engine continuously monitors traffic conditions and adjusts the clock source accordingly, optimizing both latency and reliability based on real-time operational state.
Data Source
AI summary
A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.