Retimer Clock Handoff for Deterministic Latency and Low Jitter
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Solution Overview
Problem
Retimer circuitry experiences high latency and jitter, particularly at increased transmission distances, leading to data transmission errors, which existing technologies struggle to address effectively.
Innovation Solution
Implementing a retimer system with advanced clock generation circuitry and finite state machine (FSM) handoff circuitry to achieve deterministic latency and reduce jitter, utilizing interleaving, deserialization, serialization, and clock conversion techniques to synchronize data streams across different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If retimer circuitry is used to increase transmission range, then transmission distance is improved, but latency and jitter increase leading to data transmission errors
Solution Approach 1:
The patent implements dynamic clock domain conversion where the retimer circuitry adapts between different clock domains (first clock from transmitter, second clock for transmission) based on transmission conditions. This dynamic adaptation allows the system to maintain reliable data transmission over extended distances by synchronizing to appropriate clock domains, thereby resolving the contradiction between extended transmission range and data accuracy.
Solution Approach 2:
The patent changes the clock frequency parameter by generating multiple receiver clocks with different phase shifts and selectively using them based on transmission distance and signal quality. This parameter change enables the retimer to optimize performance for different transmission scenarios, maintaining data integrity while extending transmission range.
2Length of stationary object
If retimer circuitry converts data between different clocks, then transmission range is extended, but latency becomes non-deterministic
Solution Approach 1:
The patent generates multiple receiver clocks with predetermined phase shifts before data conversion is needed. This preliminary preparation of clock options allows the handoff circuitry to quickly select the appropriate clock domain without introducing variable latency, thereby maintaining deterministic timing while extending transmission range.
Solution Approach 2:
The patent segments the clock generation into multiple discrete receiver clocks with fixed phase relationships. This segmentation allows the system to pre-establish timing relationships and select from discrete clock options, ensuring deterministic latency during clock domain conversion while supporting extended transmission ranges.
3Reliability
If multiple receiver clocks with different phase shifts are generated, then jitter is reduced, but device complexity increases
Solution Approach 1:
The clock generation circuitry is designed to generate multiple receiver clocks with different phase shifts using a unified architecture. This multi-functional clock generator serves multiple purposes: providing phase diversity for jitter reduction, enabling deterministic latency through pre-established relationships, and supporting various transmission scenarios, thereby achieving jitter reduction without proportionally increasing overall device complexity.
Data Source
AI summary
An example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.