Retimer Clock Switchover Without Domain-Crossing Latency
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Solution Overview
Problem
Conventional retimer architectures face significant latency penalties due to domain crossing between receive and local clock domains, which disrupts the seamless clock switchover process.
Innovation Solution
The implementation of a seamless-clock-switchover (SCS) retimer that alternately selects a core clock signal from two or more plesiochronous or mesochronous clock sources, ensuring that the clock switchover occurs without disrupting the edge-to-edge core clock period or duty cycle, thereby avoiding substantial latency penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional retimer architectures use separate receive and local clock domains, then clock sources can be independently managed, but latency penalties occur due to domain crossing disruptions
Solution Approach 1:
The patent merges the receive clock and local clock into a single unified clock domain, eliminating the need for clock domain crossing. The retimer operates entirely in the receive clock domain, with the local clock serving as a backup that can be seamlessly switched to without domain transition penalties, thus resolving the latency issue while maintaining independent clock source management capability
Solution Approach 2:
The patent introduces a clock switchover mechanism with phase alignment detection as an intermediary between the receive clock and local clock domains. This mediator ensures that when switching between clock sources, the transition occurs at aligned phase boundaries, preventing disruption to the core clock period and eliminating latency penalties associated with domain crossing
2Reliability
If clock switchover is implemented between receive and local clock domains, then redundancy is achieved, but edge-to-edge clock period disruption occurs causing latency
Solution Approach 1:
The patent implements phase alignment detection and adjustment mechanisms that ensure the receive clock and local clock are synchronized to the same phase reference before switchover. This equipotential approach ensures that when the clock source switches, both clocks are at equivalent phase states, preventing any disruption to the edge-to-edge clock period and eliminating latency penalties
Solution Approach 2:
The patent dynamically adjusts the phase parameter of the local clock to match the receive clock phase before switchover occurs. By changing the phase parameter of one clock to align with the other, the system ensures seamless transition without disrupting the core clock period, thus maintaining reliability while avoiding latency
3Loss of time
If receive clock is used throughout the symbol progression path, then latency is minimized, but clock stability may be compromised during receive clock drop-out
Solution Approach 1:
The patent prepares the local clock in advance by maintaining it as a ready backup with its phase alignment capability. When receive clock drop-out occurs, the pre-prepared local clock can immediately take over without causing latency, as the switchover mechanism is already in place and the local clock has been maintained in a synchronized state
Solution Approach 2:
The patent implements a dynamic clock selection mechanism that adaptively switches between the receive clock and local clock based on real-time conditions. The system dynamically monitors receive clock health and automatically transitions to the local clock when drop-out is detected, while maintaining the ability to switch back when the receive clock recovers, thus ensuring both low latency and clock stability
Data Source
AI summary
A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.