High-Speed Retimer Equalizer Adaptation and Data Rate Detection
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Solution Overview
Problem
Conventional SDI re-timers/re-clockers face challenges in accurately detecting data rates and ensuring sufficient equalization due to signal distortion and pathological data patterns, leading to unreliable operation and errors in high-speed data transmission.
Innovation Solution
A digital implementation using data transition density (DTD) and single-bit transition (SBT) tracking circuitry, which averages and maximizes measurements to immunize against pathological patterns, determining equalization levels and data rates, and employing a state machine to control equalization settings and clock rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional analog energy-based techniques are used to detect data rate, then the system can operate without reference clock, but the detection is susceptible to errors from pathological data patterns and filter offsets
Solution Approach 1:
The patent replaces the conventional analog energy-based detection system with a digital data transition tracking system. Instead of using analog filters and rectifiers to measure energy at various frequency bands, the invention uses digital circuitry to count data transitions (edges) in the received signal. This substitution of digital for analog processing eliminates susceptibility to analog component offsets and improves reliability while maintaining the ability to detect multiple data rates including pathological patterns.
2Adaptability or versatility
If the system supports all SMPTE data rates without reference clock, then the adaptability is improved, but the measurement precision deteriorates due to signal distortion and pathological patterns
Solution Approach 1:
The patent implements a feedback mechanism where the data transition density measurements are continuously monitored and used to adjust the equalization settings and confirm data rate detection. The system measures transitions over multiple intervals, compares results against expected values for different data rates, and uses this feedback to verify correct operation. This feedback loop compensates for signal distortion effects and confirms accurate measurement despite channel attenuation.
Solution Approach 2:
The system performs measurements over multiple time intervals (N intervals) and uses majority voting or averaging to determine the final data rate. Instead of relying on a single measurement that might be affected by temporary signal conditions or pathological patterns, the invention takes excessive measurements and uses the consensus of multiple readings to determine the true data rate, thereby improving measurement precision.
3Speed
If the equalizer adaptation time is reduced to within one video frame, then the speed is improved, but the reliability deteriorates due to pathological data patterns affecting lock-in
Solution Approach 1:
The patent performs preliminary data transition tracking and equalization adjustment before the CDR lock-in process begins. By pre-adapting the equalizer settings based on initial data transition density measurements, the system prepares the signal path in advance to handle upcoming pathological patterns. This preliminary action ensures that when the CDR attempts lock-in, the signal is already optimally equalized, improving reliability while maintaining fast adaptation within one video frame.
Solution Approach 2:
The system dynamically adjusts equalization settings during the adaptation period based on real-time data transition measurements. Rather than using fixed equalization parameters, the invention continuously monitors transition density and adjusts equalizer coefficients dynamically to compensate for channel effects and pathological patterns as they occur, enabling both fast adaptation and reliable lock-in.
Data Source
AI summary
Systems, circuitry and methods measure data transition metrics of incoming data, average the measurements of each metric at a set time interval for multiple intervals to generate multiple averaged values, and select a maximum of the multiple averaged values for each metric. The maximum values of each measurement cycle are compared with corresponding multiple thresholds defining respective ranges, and the outputs are used by a state machine to determine an equalization level and the rate of the incoming data. When the thresholds are not met, the state machine adjusts the equalization level, and when a sub-rate is detected using a third threshold for one of the metrics, the clock rate is also adjusted. Locking of a clock and data recovery (CDR) circuit is attempted when the maximum values for each metric are within their respective ranges.


