Multi-mode Retimer Latency and Error Detection

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Solution Overview

Problem

Current interconnect architectures face challenges in supporting high-performance computing demands, particularly in server systems, where increased processing power leads to complex communication requirements between multiple processors, and existing retimers may introduce latency and interoperability issues due to their limited capabilities in handling link states and error detection.

Innovation Solution

The development of a multi-mode retimer with advanced speed detection logic and in-band disconnect/reconnect detection, which can dynamically adjust its operating modes to minimize latency and improve error detection, enabling efficient communication across high-speed links and supporting various connection speeds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional retimers are used in interconnect architectures, then basic signal transmission is achieved, but latency increases and error detection capability deteriorates

Engineering Contradiction:
Improveerror detection capabilityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The retimer dynamically adjusts its operating parameters including latency compensation values based on detected link conditions and speed changes. The device transitions between different operational states (e.g., L0, L0s, L1) and modifies its timing characteristics in real-time to optimize both latency and error detection performance under varying connection conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The retimer changes its operational parameters such as speed detection thresholds, latency compensation values, and equalization settings based on the detected link speed and quality. This allows the device to adapt its error detection sensitivity and timing characteristics to match the current interconnect conditions, improving reliability without excessive latency penalty.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If retimers operate at fixed speeds, then simple design is maintained, but adaptability to different connection speeds deteriorates

Engineering Contradiction:
Improvespeed detection capabilityVSAvoidretimer design complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The retimer performs preliminary speed detection and link training before normal data transmission begins. It pre-negotiates the link speed with connected devices and prepares appropriate timing and equalization parameters in advance, allowing the device to adapt to different speeds without requiring complex real-time adjustments during data transmission.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The retimer implements feedback mechanisms that continuously monitor link quality and speed characteristics, then adjust its operational parameters accordingly. This feedback loop enables the device to maintain optimal performance across different connection speeds while keeping the base design relatively simple, as the complexity is managed through automated control rather than hardware variants.

Inventive Principle:
Principle #23Feedback

3Reliability

If disconnect detection is not implemented, then device complexity is reduced, but communication reliability deteriorates

Engineering Contradiction:
Improveconnection status detectionVSAvoidretimer logic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The retimer implements self-service monitoring where it continuously checks its own operational status, link integrity, and connection state without requiring external management. The device autonomously detects disconnect conditions through built-in monitoring of training sequences, idle patterns, and error rates, then triggers appropriate recovery or error reporting actions without additional control logic.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11675003B2Interconnect retimer enhancements
Publication Date: 2023.06.13 INTEL CORP
  • US11675003B2 patent drawing
  • US11675003B2 patent drawing
  • US11675003B2 patent drawing

AI summary

A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.