Retimer Link Management Using In-Band Ordered Sets

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing retimers in interconnects lack proactive link management capabilities, particularly in low-latency modes, leading to potential data corruption and reduced platform reliability due to the inability to report parity errors and participate in predictive error management.

Innovation Solution

Enhanced retimer mechanisms that manipulate Control SKP Ordered Sets (OS) to initiate link management handshakes, allowing proactive error reporting and retraining requests, even in low-latency modes, through in-band and sideband mechanisms, and include error logging capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If retimers operate in low-latency mode to improve data transmission speed, then productivity increases, but reliability deteriorates due to inability to report parity errors and participate in predictive error management

Engineering Contradiction:
Improvedata transmission speedVSAvoidplatform reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the retimer's operational capabilities by implementing separate error detection and reporting pathways for low-latency and non-low-latency modes. In low-latency mode, the retimer processes data packets without interruption while error checking continues independently, allowing speed maintenance while error management functions remain active through dedicated hardware logic that operates in parallel with the data path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary error detection and logging capabilities that continuously monitor data integrity even during low-latency operations. The retimer performs parity checks and logs potential errors in advance before they can cause data corruption, enabling proactive error management that prepares the system for corrective actions without interrupting the high-speed data flow.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If retimers manipulate Control SKP Ordered Sets to initiate link management handshakes for better error management, then reliability improves, but device complexity increases

Engineering Contradiction:
Improvelink management capabilityVSAvoidretimer complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the retimer multi-functional by enabling it to perform both data transmission and link management functions. The retimer can manipulate Control SKP Ordered Sets to initiate link management handshakes, request retraining, and report errors while simultaneously maintaining its primary data forwarding function. This universal capability allows a single device to handle multiple tasks that would traditionally require separate components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The retimer is designed to autonomously perform link management tasks without requiring external intervention. It can independently detect link errors, initiate retraining sequences by manipulating Control SKP Ordered Sets, and manage its own operational state transitions. This self-service capability reduces the need for complex external control logic while improving link reliability.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP3734463B1Retimer mechanisms for in-band link management
Publication Date: 2025.12.17 INTEL CORP
  • EP3734463B1 patent drawingFigure 1
  • EP3734463B1 patent drawingFigure 2A
  • EP3734463B1 patent drawingFigure 2B

AI summary

A retimer apparatus (204, 206) can include a receiver circuit implemented at least partially in hardware; a configuration register (256, 258) comprising a link management bit set, and one or more bit fields for link management bits indicating link management information; bit stream logic implemented at least partially in hardware to encode an ordered set (OS) with one or more link management bits from the configuration register (256, 258); and a transmitter circuit implemented at least partially in hardware to transmit OS with the one or more link management bits across a link.