Retimer Loopback PHY Layout for Ultra-Low Signal Latency
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Solution Overview
Problem
Existing retimers suffer from significant signal latency due to long distances between physical layer modules, Flip-Flops delays, and extensive digital logic areas, which are not adequately addressed by current optimization methods.
Innovation Solution
A low latency retimer design with loopback data paths and adjacent signal receiving and transmitting units on the same physical layer module, utilizing a data selector and data path logic processing units to enable ultra-low latency bypass paths, reducing signal propagation distance and skipping unnecessary conversion logics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional retimer design with separate PHY modules on opposite sides is used, then signal receiving and transmitting functions are separated, but signal latency increases due to long propagation distance
Solution Approach 1:
The patent merges the signal receiving unit and signal transmitting unit onto the same physical layer module, eliminating the long distance propagation between separate PHY modules. This integration directly reduces signal latency while maintaining the functional separation of receiving and transmitting operations through distinct unit design.
Solution Approach 2:
The patent segments the physical layer module into distinct signal receiving units and signal transmitting units, allowing independent optimization of each function while placing them in close proximity. This segmentation enables low-latency signal propagation within the same module while maintaining functional independence.
2Reliability
If multiple Flip-Flops are used for clock compensation and deskewing, then signal synchronization is improved, but device area increases and latency increases
Solution Approach 1:
The patent extracts the essential synchronization function from the complex array of Flip-Flops and implements it through a simplified phase aligner mechanism. This extraction maintains signal synchronization reliability while dramatically reducing the digital logic area and associated latency.
Solution Approach 2:
The patent changes the implementation approach from using multiple Flip-Flops (traditional parameter) to using a phase aligner with optimized clock compensation (new parameter). This parameter change achieves the same synchronization reliability with reduced complexity and lower latency.
3Adaptability or versatility
If data path logic processing units are included for normal mode operation, then signal processing capability is improved, but signal latency increases due to additional processing stages
Solution Approach 1:
The patent implements a dynamic data path selection mechanism that can switch between normal mode (through data path logic processing units) and low latency mode (bypassing processing units). This dynamic configuration allows the system to adapt between signal processing capability and low latency requirements based on operational needs.
Solution Approach 2:
The patent creates a bypass path that allows signals to skip the data path logic processing units when low latency is required. This skipping mechanism enables direct signal transmission from the signal receiving unit to the signal transmitting unit, eliminating processing delay while maintaining the option to use full processing capability when needed.
Data Source
AI summary
A low latency retimer and a low latency control method are provided; a physical layer module is provided on each of two opposite sides of the retimer; each physical layer module includes at least one set of signal transceiver units including a signal receiving unit and a signal transmitting unit; the signal receiving unit performs a serial-to-parallel conversion on a first high-speed serial signal to generate a parallel signal, and sends the parallel signal to the signal transmitting unit; the signal transmitting unit performs a parallel-to-serial conversion on the parallel signal, to convert the parallel signal to obtain a second high-speed serial signal, and outputs the second high-speed serial signal. Data paths of the retimer form a loopback structure, and the signal transmitting unit and the signal receiving unit are physically adjacent to each other, which solves the problem of signal transmission delay, and avoids high power consumption.