Retimer PLL Switching for Fast Link Rate Changes
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Solution Overview
Problem
Current retimer technologies experience significant internal delays due to long link equalization times, which are exacerbated by the need for frequent rate changes in high-speed communication scenarios like self-driving and facial recognition, and are costly to implement with low-loss panels.
Innovation Solution
A retimer system with multiple phase locked loops that dynamically adjusts operating parameters and switches between unused phase locked loops to minimize delay during rate changes, enabling transparent signal transmission without serial-to-parallel conversion, coding, or decoding, thereby reducing processing delays and bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If transparent transmission is implemented without serial-to-parallel conversion, coding, or decoding, then signal transmission delay is reduced, but link equalization becomes more challenging
Solution Approach 1:
The patent divides the phase locked loop function into multiple independent phase locked loops (at least two). Each phase locked loop can be independently configured and switched, allowing the system to maintain transparent transmission while providing dedicated resources for link equalization without requiring complex processing of the transmitted signal.
Solution Approach 2:
The patent pre-configures multiple phase locked loops with different operating parameters before transmission begins. When rate changes are needed, the system can immediately switch between pre-configured loops without performing complex real-time equalization processing, thus reducing delay while maintaining link quality.
2Productivity
If multiple phase locked loops are used for rate changing, then rate adaptation speed is improved, but device complexity increases
Solution Approach 1:
The patent designs the multiple phase locked loops to share common configuration interfaces and control mechanisms. The link adjustment circuit can uniformly manage multiple loops through standardized procedures, reducing the complexity increase that would normally result from having multiple independent loops.
Solution Approach 2:
The patent implements dynamic switching between phase locked loops based on real-time link status information. The system can adaptively select which loop to use for different transmission rates, enabling fast rate adaptation while keeping the control logic relatively simple through automated decision-making.
3Reliability
If link adjustment is performed during transmission, then transmission quality is maintained, but transmission delay increases
Solution Approach 1:
The patent pre-configures multiple phase locked loops with different operating parameters before transmission begins. When rate changes are needed, the system can immediately switch between pre-configured loops without performing complex real-time equalization processing, thus reducing delay while maintaining link quality.
Solution Approach 2:
The system automatically monitors link status information and performs switching between phase locked loops without requiring external intervention or complex processing. The link adjustment circuit self-manages the switching based on predetermined criteria, minimizing the time required for quality maintenance operations.
Data Source
AI summary
A retimer is provided. The retimer includes: a data channel circuit, configured to implement, under a function of a current phase locked loop, equalization processing-based transparent transmission of a signal between a first communications device and a second communications device; and the link adjustment circuit, configured to: when determining, based on link status information of the data channel circuit, that a rate of a link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate; and switch the currently used phase locked loop to the target phase locked loop when detecting that the link enters a rate-changing state, where the data channel circuit is further configured to implement, under a function of the target phase locked loop, the transparent transmission of a signal between the first communications device and the second communications device.