Transmitter Retimer Compensation for Power Network Jitter
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Solution Overview
Problem
High-speed bus interfaces in electronic devices experience jitter due to noise in power distribution networks, which affects signal integrity and timing margins, leading to errors in data transmission.
Innovation Solution
A transmitter circuit with a retimer circuit configuration that interleaves even and odd data bits into separate bitstreams, using a replica retimer circuit to generate a compensation bitstream, and line driver circuits to transmit these bitstreams over a communication link, ensuring deterministic power supply noise by aligning signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed data transmission is implemented, then communication speed and bandwidth are improved, but signal integrity deteriorates due to jitter and timing errors
Solution Approach 1:
The patent applies preliminary action by generating a compensation bitstream in advance that predicts and counteracts power supply noise effects before they affect the main data transmission. The replica retimer circuit pre-processes inverted data to create a compensation signal that will offset upcoming noise interference, thereby maintaining signal integrity at high transmission speeds.
Solution Approach 2:
The patent converts the harmful effect of power supply noise into a beneficial compensation mechanism. By intentionally generating a compensation bitstream that mirrors the expected noise pattern, the system transforms the predictable harmful effect into a useful correction signal that when combined with the main data stream, eliminates jitter and timing errors.
2Productivity
If retimer circuits are used to serialize data, then data transmission capability is improved, but power supply noise and jitter are generated
Solution Approach 1:
The patent introduces an intermediary compensation path with a replica retimer circuit that does not directly transmit data but generates a compensation signal. This intermediary circuit processes inverted data to create a noise profile that mediates between the main data path and the power supply network, allowing the system to tolerate higher noise levels while maintaining data integrity.
Solution Approach 2:
The patent uses copying by creating a replica retimer circuit that duplicates the functionality of the main retimer. This copy processes inverted data to generate a compensation bitstream that mirrors the noise characteristics of the main circuit, enabling precise cancellation of power supply noise effects without requiring direct modification of the primary data path.
3Measurement precision
If timing margins are tightened to handle high-frequency signals, then signal accuracy is improved, but the system becomes more susceptible to jitter errors
Solution Approach 1:
The patent implements feedback by using the compensation bitstream to continuously counteract the effects of power supply noise on the main data stream. The replica retimer circuit monitors the same data patterns and generates real-time compensation signals that feed back into the transmission system, dynamically adjusting for noise variations and maintaining timing accuracy even with tight margins.
Data Source
AI summary
A transmitter in an interface circuit includes a first retimer circuit configured to serialize data by interleaving even bits of the data and odd bits of the data into a first bitstream, a second retimer circuit configured to serialize the data by interleaving even bits of the data and inverted versions of the odd bits of the data into a second bitstream, and line driver circuits configured to transmit the first bitstream over a communication link.