Retimer Transparent Transmission for PCIe Delay Reduction
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Solution Overview
Problem
The existing retimer systems in PCIe bus applications introduce significant delay, which is unacceptable in high-speed applications like PCIe memory scenarios, due to the additional delay introduced by each retimer level, impacting system performance.
Innovation Solution
A retimer application system that includes a primary chip, a secondary chip, and a retimer, where the retimer stores equalization parameters during link training and enters a low-delay mode by bypassing data processing circuits, allowing transparent transmission of training and service data between the chips, reducing overall transmission delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If a retimer is added to extend PCIe bus connection, then link transmission distance is improved, but transmission delay increases by 40ns to 68ns per retimer level
Solution Approach 1:
The retimer performs link training and equalization parameter optimization in advance during the first link training phase. The optimized equalization parameters are stored in non-volatile memory before the reset operation. When the second link training is triggered after reset, the retimer can quickly apply the pre-stored parameters, reducing the time penalty associated with retimer intervention.
Solution Approach 2:
The retimer copies and stores the equalization parameters from the first link training session into non-volatile memory. This copied parameter set is then reused during the second link training after reset, avoiding the need to perform complete equalization again and reducing overall training time and delay.
2Reliability
If retimer performs complete link training to ensure signal quality, then link compensation capability is improved, but training time and system performance are reduced
Solution Approach 1:
The retimer performs complete link training and equalization optimization in advance during the first link training phase. The optimized equalization parameters are stored in non-volatile memory before the reset operation. When the second link training is triggered after reset, the retimer can quickly apply the pre-stored parameters, reducing the time penalty associated with retimer intervention.
Solution Approach 2:
The retimer changes its operational state by switching from active participation in link training to transparent transmission mode. By storing equalization parameters in non-volatile memory and reusing them, the retimer maintains link compensation capability while reducing the time required for repeated training sequences after reset operations.
3Reliability
If retimer processes data through complete data processing circuits to ensure signal integrity, then signal quality is improved, but transmission delay increases
Solution Approach 1:
The patent extracts the equalization parameter optimization function from the data processing path. By performing equalization parameter optimization during link training and storing results in non-volatile memory, the retimer removes the need for repeated complex signal processing during normal data transmission, thereby reducing processing delay while maintaining signal integrity through the use of pre-optimized parameters.
Solution Approach 2:
The retimer performs complete link training and equalization optimization in advance during the first link training phase. The optimized equalization parameters are stored in non-volatile memory before the reset operation. When the second link training is triggered after reset, the retimer can quickly apply the pre-stored parameters, reducing the time penalty associated with retimer intervention.
Data Source
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AI summary
This application provides a retimer application system, to help reduce a transmission delay. The application system includes a primary chip, a retimer, and a secondary chip. After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation. The retimer is further configured to: receive a reset indication, and perform the reset operation according to the reset indication. The primary chip and the secondary chip are configured to perform second link training triggered by the reset indication. During the second link training, the retimer is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter, to complete the second link training between the primary chip and the secondary chip.