Retiming Digital Circuits with Functional Equivalence Constraints
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Solution Overview
Problem
Existing circuit design optimization techniques, such as retiming, often fail to preserve functional equivalence when moving registers or latches in digital circuits, leading to suboptimal performance and increased complexity.
Innovation Solution
The introduction of a functional equivalence constraint as a top priority in the retiming process, ensuring that the modified model maintains the same functionality as the original, by analyzing conditions such as zero initial values, zero input outputs, and no state changes, allows for safe movement of delay blocks and subsequent optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If retiming is applied to optimize circuit performance and area, then productivity and device complexity are improved, but functional equivalence may be lost leading to reliability deterioration
Solution Approach 1:
The patent applies preliminary anti-action by establishing functional equivalence constraints before performing retiming operations. The method pre-identifies conditions that would violate functional equivalence (such as state changes in combinational logic) and prevents retiming moves that would cause such violations, thereby maintaining reliability while enabling optimization.
Solution Approach 2:
The patent implements feedback mechanisms by continuously checking functional equivalence constraints during the retiming process. The system monitors whether retiming operations maintain the required functional behavior and adjusts the retiming strategy accordingly, ensuring that optimization does not compromise circuit functionality.
2Reliability
If functional equivalence constraints are enforced during retiming, then reliability is maintained, but device complexity and difficulty of detection increase
Solution Approach 1:
The patent segments the functional equivalence verification into distinct checkable conditions: zero initial value verification, zero input output verification, and state change verification. This segmentation breaks down the complex functional equivalence problem into manageable sub-tasks that can be independently evaluated during retiming.
Solution Approach 2:
The patent changes the approach from verifying general functional equivalence to checking specific parameter conditions (initial values, input-output relationships, state changes). By transforming the verification problem into parameter-based checks, the system maintains reliability while reducing the complexity of the verification process.
3Productivity
If retiming moves are applied without functional equivalence checks, then productivity increases, but measurement precision and manufacturing precision decrease
Solution Approach 1:
The patent performs preliminary actions by establishing functional equivalence constraints and verification rules before executing retiming operations. This preliminary setup enables rapid verification during the retiming process, maintaining high productivity while ensuring precision through pre-defined checkable conditions.
Data Source
AI summary
A system and method tests for functional equivalence prior to automatically retiming a high-level specification. An Intermediate Representation (IR) includes one or more graphs or trees based on the high-level specification. A functional equivalence (FE) analyzer determines whether one or more components in the graph meet certain value and state conditions and thus is a candidate for retiming. A scheduler can use components that fail FE as a retiming boundary.