Retiming Pipeline Stripe Self-Gating for Lower Clock Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In large retiming pipelines, each stage has only one clock gating cell to control multiple registers, leading to inefficient power consumption as not all registers toggle at the same clock cycle, and existing self-gating solutions increase circuit area.
Innovation Solution
Implementing stripe-based self-gating by generating a change detect signal from the first stage of registers and using it as a clock-enable signal for subsequent stages, reducing power consumption without the need for additional self-gating circuitry in those stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If one clock gating cell is used to control multiple registers in each stage, then device complexity is reduced, but power consumption efficiency deteriorates because not all registers toggle at the same clock cycle
Solution Approach 1:
The circuit is divided into stripes, with each stripe containing multiple stages. Within each stripe, the first stage implements self-gating while subsequent stages share the clock enable signal, creating a segmented approach that balances complexity and power efficiency across different regions of the circuit.
Solution Approach 2:
The clock enable signal generated from the first stage serves multiple functions: it acts as the clock enable for all subsequent stages within the same stripe, and can be shared across multiple registers in those stages. This multi-functional signal reduces the total number of clock gating cells needed while maintaining power efficiency.
2Use of energy by moving object
If self-gating circuitry is added to each stage to reduce power consumption, then power consumption is reduced, but circuit area increases
Solution Approach 1:
Self-gating circuitry is selectively applied only to the first stage of each stripe rather than every stage. This segmentation strategy reduces the total amount of self-gating logic required while still achieving power savings across the entire circuit through the shared clock enable mechanism.
Solution Approach 2:
Multiple stages within a stripe share a common clock enable signal generated from the first stage. By merging the clock control function across multiple stages, the patent eliminates the need for separate self-gating circuitry in each subsequent stage, thereby reducing overall circuit area while maintaining power efficiency.
Data Source
AI summary
Systems, apparatuses, and methods for implementing stripe-based self-gating and change detect signal propagation for retiming pipelines are disclosed. A circuit includes one or more stripes, with each stripe including a plurality of stages of registers, with each stage only receiving input signals from the preceding stage. For a given stripe, the first stage of registers are self-gated to reduce power consumption by only clocking a group of registers when any of their input signals change. The self-gating signals of the first stage of registers are combined together to create a change detect signal which is passed through a register and provided to a second stage of registers as a clock-enable signal. Accordingly, the second stage registers are only clocked when the change detect signal indicates a change will be forwarded from the first stage. This reduces power consumption for the second stage without causing the area increase associated with self-gating circuitry.