Retired Memory Rows for Non-Mission-Critical Data Storage

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Solution Overview

Problem

Memory devices, such as DRAM, face challenges in managing defective memory rows, where traditional error correction techniques are insufficient to handle physical defects, leading to the need for post-package repair (PPR) operations that retire entire rows despite most storage being usable.

Innovation Solution

The implementation of a memory controller that determines the suitability of retired memory rows for storing non-mission-critical data by evaluating the number of defective bits and using error masks to avoid writing data to defective locations, thereby reclaims storage capacity that would otherwise be unused.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional error correction techniques are used to handle defective memory rows, then reliability is improved, but storage capacity is lost because entire rows must be retired

Engineering Contradiction:
Improvedefect handling capabilityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the memory row into usable and defective portions, allowing only the defective bits to be masked while the remaining functional bits continue to store data. This is achieved by creating a row mask that selectively disables only the defective bit locations rather than retiring the entire row, thus resolving the contradiction between reliability and storage capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by treating different portions of the memory row differently - defective bits are masked out while functional bits remain accessible for storage. The row mask mechanism allows selective degradation of only the necessary portions (defective bits) while preserving the quality and functionality of the remaining bits, thereby maintaining both reliability and maximizing storage capacity.

Inventive Principle:
Principle #3Local quality

2Reliability

If entire memory rows are retired due to physical defects, then reliability is improved, but storage capacity is reduced

Engineering Contradiction:
Improvedefect managementVSAvoidusable storage space
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent discards only the defective portions of memory rows by masking specific bad bits, while recovering and utilizing the remaining functional portions for data storage. This selective discarding approach recovers a significant portion of what would otherwise be lost storage capacity, resolving the contradiction between reliable defect management and usable storage space.

Inventive Principle:
Principle #34Discarding and recovering

3Reliability

If post-package repair operations are performed to retire defective rows, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedefect correctionVSAvoidrepair process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by identifying and masking defective bits during the manufacturing test phase before the device is shipped. The row mask information is stored in non-volatile memory and automatically applied during normal operation, eliminating the need for complex post-package repair operations and reducing device complexity while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250061055A1Storage of data using retired memory rows
Publication Date: 2025.02.20 MICRON TECHNOLOGY INC
  • US20250061055A1 patent drawing
  • US20250061055A1 patent drawing
  • US20250061055A1 patent drawing

AI summary

Methods, apparatuses, and systems related to storing non-mission-critical data using retired memory slots are described. An apparatus includes circuitry configured to determine that a post package repair (PPR) operation, associated with a memory row of a memory device, has been requested by a host device communicably coupled to the circuitry. The memory row is associated with a physical address. The circuitry determines a location of a defective bit in the memory row. Retired row data comprising the physical address associated with the memory row and the defective bit location is maintained in non-transitory memory of the apparatus.