Retractable Interprocessor Interrupts via Special Purpose Registers
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Solution Overview
Problem
Interprocessor interrupt handling in electronic systems is inefficient due to high latency and overhead, particularly when using external interrupt mechanisms, which can be undesirable for smaller tasks and may not be justified for tasks that are not economically large enough.
Innovation Solution
Implementing special purpose registers (SPRs) such as model specific registers (MSRs) to communicate interprocessor interrupts (IPIs) directly between processors, reducing latency and allowing for different types of IPIs like immediate, deferred, retract, and non-waking, which provide flexibility in interrupt handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external interrupt mechanism is used for IPI transmission, then interrupt handling is standardized, but latency increases and overhead increases
Solution Approach 1:
The patent extracts the IPI transmission mechanism from the general external interrupt controller and implements a dedicated IPI transmission path using special purpose registers. This separation removes IPIs from the standardized but slower external interrupt handling path, achieving lower latency while maintaining reliability for IPI-specific operations.
Solution Approach 2:
The patent introduces special purpose registers as an intermediary mechanism between processors for direct IPI transmission. These registers serve as a dedicated communication channel that bypasses the external interrupt controller, reducing latency while maintaining standardized interrupt handling through the register interface.
2Device complexity
If external interrupt controller is used for IPI, then interrupt prioritization is handled centrally, but transmission overhead increases
Solution Approach 1:
The patent extracts IPI transmission from the centralized external interrupt controller and implements it through dedicated special purpose registers. This extraction reduces the overhead of centralized control for IPIs specifically, while the interrupt controller remains available for other external interrupts.
Solution Approach 2:
The patent segments the interrupt handling system into two paths: a dedicated IPI path using special purpose registers for low-latency processor-to-processor communication, and a general external interrupt path using the interrupt controller for other devices. This segmentation allows optimized handling for IPIs without compromising centralized control for other interrupts.
3Speed
If immediate IPI is used for task assignment, then task notification is fast, but processor must wake from sleep state
Solution Approach 1:
The patent implements dynamic IPI types that allow the system to adapt to different power states. The retractable IPI mechanism allows deferred task assignment that can be canceled or delayed if the processor remains in sleep state, enabling fast task notification when needed while conserving energy when processors are idle.
Solution Approach 2:
The patent uses retractable IPIs to perform preliminary task assignment notifications that can be canceled if the processor is sleeping. This allows the system to prepare for fast task assignment when processors are active, while avoiding unnecessary wake-ups and energy consumption when processors are in low-power states.
4Adaptability or versatility
If deferred IPI is used to delay interrupt, then task timing is flexible, but latency cannot be precisely controlled
Solution Approach 1:
The patent implements a feedback mechanism with retractable IPIs that allows the system to monitor processor state and adjust interrupt delivery timing. The ability to retract or cancel deferred IPIs provides feedback control over interrupt timing, enabling precise timing when needed while maintaining flexibility for deferred execution when appropriate.
Data Source
AI summary
In an embodiment, processors may have associated special purpose registers (SPRs) such as model specific registers (MSRs), used to communicate IPIs between the processors. In an embodiment, several types of IPIs may be defined, such as one or more of an immediate type, a deferred type, a retract type, and/or a non-waking type. The immediate IPI may be delivered and may cause the target processor to interrupt in response to receipt of the IPI. The deferred IPI may be delivered within a defined time limit, and not necessarily on receipt by the target processor. The retract IPI may cause a previously transmitted IPI to be cancelled (if it has not already caused the target processor to interrupt). A non-waking IPI may not cause the target processor to wake if it is asleep, but may be delivered when the target processor is awakened for another reason.