Retry Mechanism for Cache Coherency in Multi-Processor Systems
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Solution Overview
Problem
In systems with cache coherent communication among processors, long memory latencies lead to inefficient storage needs and complications in ensuring proper function without deadlock or loss of coherency, particularly when multiple devices attempt to share a cache block, resulting in wasted bandwidth and increased power consumption due to repeated retries of transactions.
Innovation Solution
An interface unit with a buffer and control unit that records and inhibits reinitiation of transactions until a specific identifier is detected on the interconnect, preventing unnecessary retries and optimizing bandwidth usage by linking transactions only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transactions are retried when cache blocks are shared by multiple processors, then cache coherency is maintained, but bandwidth is wasted and power consumption increases
Solution Approach 1:
The system performs preliminary actions by recording promises in advance when a processor indicates it will provide a cache block. This allows the system to proactively track which processors have committed to providing data, eliminating the need for repeated retry transactions and reducing power consumption while maintaining coherency.
Solution Approach 2:
The system implements feedback mechanisms where processors provide status information about their cache blocks through snoop requests and promises. This feedback loop allows the system to monitor cache coherency states and determine when retries are actually necessary, preventing unnecessary power consumption from redundant transactions.
2Reliability
If multiple devices form a linked list of promises to provide data, then cache coherency is ensured, but storage requirements increase
Solution Approach 1:
The invention extracts only the essential information needed for coherency management by recording simple promises indicating which processor will provide a cache block. Instead of maintaining complex linked lists with multiple data structures, the system extracts and stores only the critical promise information, significantly reducing storage requirements while ensuring coherency.
3Adaptability or versatility
If multiple processors share a cache block with long memory latencies, then system functionality is maintained, but transaction efficiency decreases
Solution Approach 1:
The system performs preliminary actions by recording promises in advance when processors indicate they will provide cache blocks. This proactive approach allows the system to prepare for future data transfers, reducing the need for repeated retry transactions and improving overall transaction efficiency while maintaining shared access capability.
Data Source
AI summary
An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.