Retry Queue Dependency for Memory Transaction Ordering
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Solution Overview
Problem
In memory systems, particularly in computer systems with hierarchical memory structures, memory transactions often face resource bottlenecks, leading to inefficiencies and potential errors due to cache management transactions being processed out of order, which can result in erroneous data access and system performance degradation.
Innovation Solution
A retry queue circuit and transaction arbiter circuit are implemented to determine if a cache management transaction is blocked by previous transactions, establishing dependencies through pseudo victim addresses to properly order retry attempts, ensuring that cache management transactions are processed only after dependent transactions are completed, thereby avoiding data errors and maintaining system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory transactions are queued for resource retry, then resource availability is improved, but transaction processing order may be incorrect causing data errors
Solution Approach 1:
The patent applies preliminary action by checking address dependencies between transactions before queuing them for retry. The system identifies whether a queued cache management transaction targets the same address as a previously queued memory transaction, and if so, establishes a dependency relationship in advance. This prevents incorrect processing order from occurring in the first place, maintaining data accuracy while allowing efficient retry queuing.
2Productivity
If cache management transactions are processed without address dependency checks, then processing speed is improved, but data errors occur due to incorrect processing order
Solution Approach 1:
The patent introduces an intermediary mechanism - the address dependency check and dependency bit - that mediates between cache management transactions and memory transactions. This intermediary layer quickly determines whether a dependency exists by comparing addresses, allowing most transactions to proceed at high speed while ensuring data accuracy for transactions that do have dependencies. The dependency bit acts as a simple flag that enables or disables the retry logic based on address matching.
3Reliability
If dependency checking is implemented for all transactions, then data accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing address dependency checking selectively rather than universally. The dependency check is performed specifically for cache management transactions that are being queued for retry, not for all memory transactions. The complexity is localized to the retry queue logic and address comparison circuitry, while the rest of the memory system continues to operate with simple first-come-first-served queuing. This targeted approach maintains data accuracy where needed while minimizing overall system complexity.
Data Source
AI summary
A memory cache controller includes a transaction arbiter circuit and a retry queue circuit. The transaction arbiter circuit may determine whether a received memory transaction can currently be processed by a transaction pipeline. The retry queue circuit may queue memory transactions that the transaction arbiter circuit determines cannot be processed by the transaction pipeline. In response to receiving a memory transaction that is a cache management transaction, the retry queue circuit may establish a dependency from the cache management transaction to a previously stored memory transaction in response to a determination that both the previously stored memory transaction and the cache management transaction target a common address. Based on the dependency, the retry queue circuit may initiate a retry, by the transaction pipeline, of one or more of the queued memory transactions in the retry queue circuit.