Information Processing Device Return Address Integrity
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Solution Overview
Problem
Existing methods fail to prevent tampering of return addresses and unauthorized branching in information processing devices, particularly during the timing between authentication code verification and return instruction execution, and are unable to detect skipped authentication code verification instructions.
Innovation Solution
An information processing device with a memory unit and processing unit that executes a determination process to verify if the instruction at a specific address is an authentication code verification instruction, and checks for match or mismatch of the authentication code after executing a return instruction, thereby detecting tampering and unauthorized branching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If authentication code verification is performed before return instruction execution, then return address integrity is protected, but vulnerability exists during the timing gap between verification completion and return instruction execution
Solution Approach 1:
The patent places an authentication code verification instruction at the return address location in advance. When a return instruction is executed, the processor automatically jumps to this pre-placed verification instruction, which then verifies the authentication code before continuing execution. This preliminary arrangement eliminates the timing gap vulnerability by ensuring verification is inherently part of the return flow path.
Solution Approach 2:
The patent implements a feedback mechanism where the authentication code verification instruction checks whether the return address matches the expected address stored in the authentication code. If there is a mismatch (indicating tampering), the verification fails and the system can take corrective action. This feedback loop ensures that any tampering attempt is detected and prevented.
2Reliability
If authentication code verification instruction is skipped with malicious intent, then attack detection is needed, but existing verification methods cannot detect skipped instructions
Solution Approach 1:
The patent pre-places the authentication code verification instruction at the return address location in the instruction sequence. This ensures that when a return instruction is executed, the processor must sequentially execute this verification instruction. Any attempt to skip or bypass this instruction would result in executing unauthorized code, which can be detected by monitoring the instruction flow or by the verification failure itself.
Solution Approach 2:
The authentication code verification instruction acts as an intermediary between the return instruction and the subsequent code execution. It serves as a gatekeeper that must be executed and pass verification before allowing normal execution to continue. This intermediary mechanism inherently detects skipped instructions because the verification step cannot be bypassed without executing unauthorized code.
3Reliability
If return address is tampered aiming at timing between verification completion and return instruction execution, then prevention becomes impossible with existing methods, but post-return verification can detect such tampering
Solution Approach 1:
The patent arranges the authentication code verification instruction at the return address location in advance, so that when a return instruction is executed, the processor automatically jumps to and executes this verification instruction before continuing. This preliminary placement ensures that any tampering of the return address is detected at the moment of return, eliminating the vulnerability window that exists in traditional methods where verification occurs before the return instruction.
Data Source
AI summary
An information processing device according to an embodiment of the present disclosure is provided with a memory unit including a stack area, and an information processing unit. The information processing unit executes, after executing a return instruction to a specific address, a determination process configured to determine whether an instruction placed at the specific address is an authentication code verification instruction, and verifies, in a case where the instruction placed at the specific address is consequently determined as the authentication code verification instruction, match or mismatch of an authentication code by executing the authentication code verification instruction.