Return Path Quality Factor Calculation for PCB Circuit Design
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Solution Overview
Problem
Current methods for evaluating return path quality in electrical circuits, such as those on printed circuit boards, are inadequate as they either rely on geometric checks that cannot accurately model the return path or full-wave simulations that are computationally intensive, making them impractical for full-board analysis.
Innovation Solution
A computer-implemented method using a processor to identify nets in an electronic circuit design, extract ideal and real loop inductances, and calculate a return path quality factor, which is a ratio of real to ideal loop inductance, allowing for visualization and graphical representation of return path quality issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometric checks are used for return path analysis, then full-board screening capability is achieved, but measurement precision of actual return path is insufficient
Solution Approach 1:
The patent segments the return path analysis into two distinct components: ideal loop inductance extraction (geometric approach for full-board screening) and real loop inductance extraction (hybrid solver approach for accuracy). By dividing the analysis into these segments, the system achieves both full-board screening capability and precise measurement of actual return path characteristics.
Solution Approach 2:
The patent introduces a hybrid solver as an intermediary between the geometric model and the actual return path analysis. This hybrid solver extracts real loop inductance by considering actual PCB stackup, material properties, and discontinuities, serving as a mediator that bridges the gap between simplified geometric checks and complex full-wave simulations.
2Measurement precision
If full-wave solvers are used to accurately model return path current, then measurement precision is improved, but device complexity and computational resources increase
Solution Approach 1:
The patent applies partial action by using the hybrid solver only for extracting real loop inductance of specific nets, rather than performing full-wave simulation across the entire PCB. This selective application of the hybrid solver provides accurate return path current modeling where needed while avoiding the excessive computational resources required for complete full-wave analysis of the entire board.
3Measurement precision
If full-wave simulation is used for return path analysis, then measurement precision is improved, but productivity decreases due to computational intensity
Solution Approach 1:
The patent segments the analysis approach by combining geometric checks (for rapid full-board screening) with hybrid solver extraction (for accurate local analysis). This segmentation allows the system to maintain high productivity through geometric checks while improving measurement precision selectively using the hybrid solver only where necessary, avoiding the productivity loss of applying full-wave simulation universally.
Data Source
AI summary
Embodiments include herein are directed towards a method for electronic circuit design and more specifically towards determining return path quality in an electrical circuit. Embodiments may include providing, using a processor, an electronic circuit design and identifying at least one net associated with the electronic circuit design. Embodiments may further include extracting an ideal loop inductance for the at least one net and extracting a real loop inductance for the at least one net. Embodiments may also include calculating a return path quality factor based upon, at least in part, the ideal loop inductance and the real loop inductance.