Return Prediction Circuit for Precise Instruction Fetch Parameters
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Solution Overview
Problem
Existing processor circuits waste bandwidth and power due to indiscriminate instruction fetching for return instructions, as next fetch predictor circuits fail to predict fetch width and bank indicators for target addresses of return instructions.
Innovation Solution
Implementing a return prediction circuit that tracks fetch parameters for return instructions, including a return address stack and prediction circuit to store and retrieve fetch parameters, optimizing instruction fetching by limiting retrieval to necessary instructions and reducing unnecessary bank accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If indiscriminate instruction fetching is performed for return instructions, then instruction fetch coverage is maintained, but bandwidth and power are wasted
Solution Approach 1:
The return prediction circuit performs preliminary action by predicting fetch parameters (fetch width and bank indicator) for return instructions before actual instruction fetching occurs. The circuit stores return addresses and their associated fetch parameters in advance, allowing the processor to skip unnecessary fetching operations and directly retrieve required instructions, thereby reducing bandwidth waste and power consumption.
Solution Approach 2:
The return prediction circuit enables self-service by autonomously determining fetch parameters for return instructions without requiring external control signals. The circuit independently predicts whether a return instruction will be taken and retrieves the appropriate fetch width and bank indicator from its internal storage, allowing the instruction fetch unit to operate efficiently without conservative over-fetching.
2Loss of energy
If fetch parameters are not predicted for return instructions, then circuit complexity is reduced, but bandwidth waste increases
Solution Approach 1:
The return prediction circuit is segmented into distinct functional components: a return address stack for storing return addresses, a prediction circuit for determining fetch parameters, and a storage unit for maintaining fetch width and bank indicator values. This segmentation allows each component to perform its specific function efficiently, reducing overall circuit complexity while enabling sophisticated prediction capabilities.
Solution Approach 2:
The return prediction circuit acts as an intermediary between the instruction fetch unit and the instruction cache. It translates return instruction addresses into specific fetch parameters (fetch width and bank indicator), mediating the fetch operation to prevent bandwidth waste without requiring complex modifications to the existing instruction fetch or execution pipelines.
3Loss of energy
If conservative fetch width is used, then power is saved, but instruction retrieval completeness is compromised
Solution Approach 1:
The return prediction circuit implements feedback by using actual branch outcome information from executed return instructions to update and refine its predictions. When a return instruction is executed, the actual fetch parameters used are fed back to the prediction circuit, which updates its stored values for that return address. This feedback mechanism ensures that future predictions are accurate, maintaining instruction fetch reliability while optimizing power consumption.
Data Source
AI summary
An apparatus includes a sequential fetch circuit configured to provide a given sequential fetch address for use in a fetch request, and a sequential prediction circuit configured to store, for one or more sequential fetch addresses, respective sets of sequential fetch parameters for use in subsequent fetch requests. The apparatus further includes a fetch control circuit configured to, based at least on retrieving a particular sequential fetch address from the sequential fetch circuit, use the particular sequential fetch address to determine whether a particular set of sequential fetch parameters exists in the sequential prediction circuit. The fetch control circuit is also configured to, based at least on a determination that the particular set of sequential fetch parameters exists, use the particular set of sequential fetch parameters to create a next fetch request to retrieve instructions starting at the particular sequential fetch address.