Return Stack Buffer Side Channel Attack Mitigation

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Solution Overview

Problem

Existing processor architectures struggle to effectively mitigate return stack buffer side channel attacks, particularly for branch predictors that do not include tag lookups, as adding context information is impractical due to management and storage requirements.

Innovation Solution

The processor employs a return stack buffer that stores return address indicators and associated exception levels. Upon a function call, the return address and exception level are stored, and upon return, the processor compares the exception level of the return with the stored exception level. If they match, the return address is used for instruction flow prediction; otherwise, it is not used.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If context information is added to return stack buffer entries to prevent side channel attacks, then security is improved, but device complexity and storage requirements increase significantly

Engineering Contradiction:
ImprovesecurityVSAvoidmanagement and storage requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the context identification function from complex context information storage and replaces it with a simple exception level indicator. Instead of storing and managing full context information (which would require complex management structures), the invention extracts only the essential exception level value that can uniquely identify the software context, thereby preventing side channel attacks without significant complexity increase

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention changes the parameter used for context identification from complex context information (requiring tag lookups and management) to a simple exception level indicator. This parameter change allows the return stack buffer to differentiate between software contexts using a lightweight mechanism that does not require impractical amounts of additional information management

Inventive Principle:
Principle #35Parameter changes

2Reliability

If exception level indicators are stored and compared in return stack buffer, then side channel attack mitigation is achieved, but information storage requirements increase

Engineering Contradiction:
Improveattack mitigationVSAvoidinformation storage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent uses lightweight exception level indicators instead of expensive full context information storage. These exception level values are simple numerical parameters that require minimal storage space compared to full context information, achieving attack mitigation with a cost-effective storage solution

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS12333001B2Mitigation of return stack buffer side channel attacks in a processor
Publication Date: 2025.06.17 AMPERE COMPUTING LLC
  • US12333001B2 patent drawing
  • US12333001B2 patent drawing
  • US12333001B2 patent drawing

AI summary

Mitigation of return stack buffer side channel attacks in a processor. Detecting a side channel attack or a fault in a return from a function call in the processor includes receiving a return exception level indication (or e.g., a return security level indication) indicating the exception level associated with the return and comparing the exception level associated with the return to the exception level (or security level) associated with the return address. The return exception level indicator may be received in conjunction with a return indication. The processing circuit accesses the first entry of the return stack buffer, which indicates the return address of the function call, and also accesses an exception level associated with the return address. The processing circuit compares the exception level associated with the return address to the exception level associated with the return to determine whether to use the return address in a prediction of instruction flow.