Reusable Carrier Structure for 3D IC Backside Processing
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the minimum feature size of integrated circuits due to process limitations, and stacking two-dimensional ICs into three-dimensional ICs is a potential solution, but existing wafer bonding processes are not efficient for high-density routing.
Innovation Solution
A carrier structure is developed comprising a semiconductor substrate with a specific layer configuration, including a release layer made of carbon-free metal nitride, which allows for clean separation from the dielectric layer using infrared laser-induced spallation, enabling efficient backside processing and reuse of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wafer bonding process with backside process is used for stacking 2D ICs into 3D ICs, then high-density routing capability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The bonding process is segmented into distinct stages: front-side bonding, backside processing, and release. The carrier substrate is separated into functional layers (bonding layer, release layer, carrier substrate) that can be independently processed and reused, reducing overall manufacturing complexity while maintaining high-density routing capability
Solution Approach 2:
The carrier substrate is designed to be reusable after release. After bonding and backside processing, the carrier substrate is recovered and can be reused for subsequent bonding operations, reducing manufacturing costs and complexity while enabling high-density routing through multiple stacking cycles
2Ease of manufacture
If conventional bonding process is used, then substrate can be processed, but substrate cannot be reused due to damage
Solution Approach 1:
A dedicated bonding layer is deposited on the carrier substrate before bonding to absorb thermal and mechanical stress during the bonding process. This protective layer cushions the carrier substrate against damage, enabling reuse while maintaining substrate integrity throughout multiple processing cycles
Solution Approach 2:
The bonding layer acts as an intermediary between the carrier substrate and the IC wafer. This intermediate layer protects the carrier substrate from direct contact with processing conditions that would cause damage, while still enabling effective bonding and subsequent release for substrate reuse
3Strength
If sophisticated bonding techniques are used, then bonding strength is improved, but manufacturing cost increases
Solution Approach 1:
The bonding process uses controlled parameter changes including temperature cycling, pressure application, and laser irradiation to achieve strong bonding. By optimizing these parameters and using a reusable carrier substrate, the process achieves high bonding strength while reducing overall manufacturing costs through substrate reuse
Solution Approach 2:
The carrier substrate enables continuous processing by being reused across multiple bonding cycles. The substrate undergoes backside processing while mounted, then is released and immediately reused for the next wafer, maintaining continuous productive action and reducing manufacturing costs per unit
4Manufacturing precision
If minimum feature size is reduced, then processing capability is improved, but process limitations prevent further shrinking
Solution Approach 1:
The patent transitions from 2D planar processing to 3D vertical stacking by bonding multiple IC wafers together. This dimensional change allows continued improvement of processing capability through increased functionality and density in the vertical dimension, bypassing the limitations of further shrinking minimum feature size in the 2D plane
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates high-density signal routing and cost-effective manufacturing by allowing for the reuse of semiconductor substrates without damage, reducing thermal stress, and minimizing manufacturing costs.
Implementation Method 1
allows for clean separation from the dielectric layer using infrared laser-induced spallation
Implementation Method 2
reducing thermal stress
Data Source
AI summary
A carrier structure and methods of forming and using the same are described. In some embodiments, the method includes forming one or more devices over a substrate, forming a first interconnect structure over the one or more devices, and bonding the first interconnect structure to a carrier structure. The carrier structure includes a semiconductor substrate, a release layer, and a first dielectric layer, and the release layer includes a metal nitride. The method further includes flipping over the one or more devices so the carrier structure is located at a bottom, performing backside processes, flipping over the one or more devices so the carrier structure is located at a top, and exposing the carrier structure to IR lights. Portions of the release layer are separated from the first dielectric layer.