Reused Submodule Voltage Consistency in Chip Design
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Solution Overview
Problem
In integrated circuit chip design, reused sub modules often exhibit timing variations due to different voltage environments, leading to increased design complexity and workload, as existing methods to address these variations are time-consuming and ineffective.
Innovation Solution
The method involves adjusting the number and location of power connection points and power wires on the power grid to ensure consistent voltage environments across reused sub modules, thereby maintaining consistent timing characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If reused sub modules are called multiple times in hierarchical design, then design complexity is reduced, but timing variation between reused sub modules increases
Solution Approach 1:
The patent applies local quality by adjusting power connection points and power wire configurations specifically for reused sub modules to ensure consistent voltage environments. Instead of uniformly treating all sub modules, the invention locally optimizes power delivery to each reused sub module instance, compensating for variations in their operational environments and thereby reducing timing variations while maintaining design reusability.
2Reliability
If logical methods are used to reduce timing variation by adjusting drive capability and threshold voltage, then timing variation is reduced, but design time increases
Solution Approach 1:
The patent changes physical parameters of the power delivery network, specifically adjusting power connection point locations, power wire widths, and power grid configurations. These parameter changes directly affect voltage environments and timing characteristics of reused sub modules, providing an alternative to logical adjustments that would require extensive re-synthesis and optimization iterations.
3Reliability
If physical methods are used to adjust module locations and power supply capacity, then timing variation is reduced, but design complexity and work load increase
Solution Approach 1:
The patent applies equipotentiality by configuring power connection points and power wires to ensure that all reused sub modules operate from consistent voltage potential levels. This creates an equipotential power delivery environment across the chip, eliminating voltage-induced timing variations without requiring complex manual adjustments to each sub module's physical location or power supply capacity.
4Reliability
If power connection points and power wires are adjusted to ensure consistent voltage environments, then timing variation is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies universality by creating a standardized power connection point configuration and power wire design that can be universally applied to all reused sub modules. This universal power delivery framework serves multiple functions: it ensures consistent voltage environments, simplifies design reuse, and provides a systematic approach that can be automatically generated by EDA tools, thereby not increasing but actually reducing manufacturing complexity.
Data Source
AI summary
The present invention discloses a method, system, and design structure for making voltage environment consistent for reused sub modules in chip design, wherein each reused sub module is connected to a power grid of the chip through power connection points on a power ring of the sub module, the method including: adjusting numbers and locations of power connection points of a plurality of reused sub modules, such that the numbers of the power connection points and locations of the corresponding power connection points are identical for the plurality of reused sub modules; adjusting power wires of the plurality of reused sub modules on the power grid which are connected the power connection points, such that voltages at the corresponding power connection points are consistent for the plurality of reused sub modules. The present invention may reduce timing variation of reused sub modules in chip design and finally achieve an objective of reducing design complexity and work load and shortening the design period.