Reverse Bias Trim for Non-Volatile Memory Resistance Control
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Solution Overview
Problem
Non-volatile memory arrays with passive element memory cells face challenges in reliable fabrication, programming, and reading due to high leakage currents, program disturbances, and resistance variations among cells, limiting bandwidth and accuracy in read and write operations.
Innovation Solution
A reverse bias trim operation is applied to non-volatile memory cells to adjust their resistance levels, where a first reverse bias sets the cells to a target resistance state, and a second, smaller reverse bias adjusts cells that are deeply reset back to the target level, ensuring consistent resistance across the array without affecting cells already at the correct level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard reset operation is applied to memory cells, then the cells transition to a higher resistance state, but some cells become deeply reset to a resistance level beyond the target, causing resistance variation and reduced reliability
Solution Approach 1:
The reset operation is divided into two distinct phases: a first reverse bias applied to all selected cells to achieve initial reset, and a second, smaller reverse bias applied only to cells that were deeply reset. This segmentation allows different cells to receive different levels of reset bias based on their individual states, preventing both under-reset and over-reset conditions while improving reliability and resistance consistency.
Solution Approach 2:
The patent applies a dynamic trim operation that detects and corrects deeply reset cells after the initial reset. By applying a second, smaller reverse bias selectively to cells that need it, the system dynamically adjusts the reset process to achieve uniform resistance levels across all cells, resolving the contradiction between rapid reset and precision control.
2Productivity
If higher bandwidth operations are implemented, then data transfer speed increases, but leakage currents and program disturbances increase, reducing operational reliability
Solution Approach 1:
The patent converts the harmful effect of reverse bias-induced resistance changes into a beneficial trimming mechanism. By applying a controlled second reverse bias to deeply reset cells, the system corrects resistance variations that would otherwise cause reliability issues, enabling higher bandwidth operations with maintained reliability through normalized resistance levels across the memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage currents, enhances operational reliability, and allows for higher bandwidth operations by normalizing resistance levels, thereby improving the performance and accuracy of memory cell operations.
Implementation Method 1
applying at least one reverse bias reset voltage to reset the storage elements from a lower resistance set state to a higher resistance reset state
Data Source
AI summary
A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.