Reverse-Biased Diode for Plasma Ion Drainage in IC
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Solution Overview
Problem
Integrated circuits face noise interference due to accumulated positive ions in deep doped wells during plasma processing, which can damage gate dielectrics and compromise signal integrity, a challenge not addressed by existing antenna design rules.
Innovation Solution
Incorporating a reverse-biased protection diode between transistors and signal lines to drain positive ions from deep doped wells, preventing them from reaching the gate dielectric and reducing plasma damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If plasma processing is used to fabricate devices and interconnects, then manufacturing capability and integration density are improved, but positive ions accumulate in deep doped wells causing gate dielectric damage and reduced device reliability
Solution Approach 1:
A diode structure is introduced as an intermediary component between the deep n-well and the gate dielectric. The diode captures and drains positive ions accumulated during plasma processing, preventing them from reaching and damaging the gate dielectric. This intermediary structure resolves the contradiction by allowing plasma processing to continue while protecting the sensitive gate dielectric from ion damage.
Solution Approach 2:
The invention converts the harmful accumulation of positive ions in deep doped wells into a beneficial effect. By intentionally creating a controlled path for ion discharge through the diode structure, the harmful ions are redirected to serve a protective function, draining away from sensitive areas and preventing gate dielectric damage. This transforms the plasma processing harm into a controlled discharge mechanism that enhances device reliability.
2Reliability
If deep doped wells are used for device isolation and functionality, then device performance is improved, but positive ion accumulation during plasma processing damages gate dielectrics
Solution Approach 1:
The diode structure serves as a protective intermediary positioned between the deep n-well and the gate dielectric. It intercepts positive ions that would otherwise travel through and damage the gate dielectric, channeling them instead to a safe discharge path. This intermediary structure allows deep doped wells to maintain their device isolation and functionality while preventing ion-induced gate dielectric damage.
3Manufacturing precision
If antenna design rules are followed to prevent plasma damage, then some gate dielectric protection is achieved, but damage from ions in deep doped wells is not addressed
Solution Approach 1:
The diode structure provides self-service protection by automatically capturing and draining positive ions that accumulate in deep doped wells during plasma processing. The structure is inherently designed to respond to ion accumulation without requiring external control or modification of existing antenna design rules. This self-service mechanism extends plasma damage protection to previously unprotected deep well structures, enhancing the versatility of plasma damage mitigation strategies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces plasma-induced damage to gate dielectrics, enhancing the reliability and yield of transistors by isolating and discharging positive ions, thereby maintaining signal integrity and device performance.
Implementation Method 1
drain positive ions from deep doped wells
Implementation Method 2
accumulated positive ions in deep doped wells during plasma processing
Implementation Method 3
discharge positive charges
Data Source
AI summary
A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.