Reverse-Biased ESD Clamp Circuit for Low-Capacitance I/O Protection
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Solution Overview
Problem
Existing ESD protection circuits for semiconductor chips face challenges in providing robust protection while maintaining low capacitive load and linearity, especially under high-speed signal conditions and modern semiconductor technology nodes with low ESD victim breakdown voltages.
Innovation Solution
The proposed ESD protection circuitry employs a dual-diode configuration with reverse-biased diodes to create a low-capacitance, over- and undervoltage-tolerant protection path. This configuration includes a first conductive path with a voltage level higher than the positive supply voltage and a second conductive path with a voltage level lower than the negative supply voltage, both coupled to a second node via capacitors, minimizing capacitive load and improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If robust ESD protection is implemented, then protection capability is improved, but capacitive load increases
Solution Approach 1:
The patent changes the biasing parameter of the diodes from forward-biased or zero-biased to reverse-biased state. This parameter change reduces the junction capacitance of the diodes significantly, thereby reducing the capacitive load on the I/O node while maintaining ESD protection capability through the reverse-biased diode clamping action.
Solution Approach 2:
The patent implements dynamic biasing of the diodes using voltage levels that are higher than the positive supply voltage and lower than the negative supply voltage. This dynamic biasing arrangement allows the diodes to operate in reverse-biased state during normal operation (reducing capacitance) while still providing ESD protection when voltage excursions occur.
2Reliability
If robust ESD protection is implemented, then protection capability is improved, but linearity deteriorates
Solution Approach 1:
By changing the biasing parameter to reverse-biased state, the diodes operate in a region with lower capacitance and improved linearity. The reverse-biased diodes present a more linear impedance to the I/O node compared to forward-biased diodes, thereby improving signal linearity while maintaining ESD protection through voltage clamping.
3Object-affected harmful factors
If low capacitive load is achieved, then signal integrity is improved, but ESD protection capability deteriorates
Solution Approach 1:
The dynamic biasing arrangement allows the diodes to switch between low-capacitance reverse-biased state during normal operation and conductive state during ESD events. The voltage levels are configured to maintain reverse-bias under normal conditions (low capacitance) while allowing forward conduction when ESD voltage exceeds the bias voltage plus diode drop.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances ESD protection while reducing the capacitive load on I/O nodes, improving signal integrity, bandwidth, and linearity, particularly for high-speed signals, and is compatible with modern semiconductor technology nodes.
Implementation Method 1
the at least one first diode is reversely biased by the first voltage level and the at least one second diode is reversely biased by the second voltage level
Data Source
AI summary
ElectroStatic Discharge (ESD) protection circuitry for a semiconductor chip. The ESD protection circuitry includes a first node for coupling to an I/O node of the semiconductor chip and includes a first conductive path coupled to the first node via a first diode. The first conductive path is configured to be at first voltage level higher than or equal to a voltage level of a first supply voltage. The ESD protection circuitry includes a second conductive path coupled to the first node via a second diode. The second conductive path is configured to be at second voltage level lower than or equal to a voltage level of a second supply voltage. The second supply voltage is lower than the first supply voltage. The ESD protection circuitry includes a second node for coupling to a ground node or a supply node of the semiconductor chip for providing the second supply voltage.