Reverse Contact Silicide Process for 3D Semiconductor Devices
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in scaling beyond two-dimensional transistor density limits, as 3D integration faces resistance, capacitance, and reliability concerns, making it difficult to achieve higher transistor density through wire pitch scaling, and existing thermal processing methods can damage metal gate materials, leading to threshold voltage shifts.
Innovation Solution
The method involves forming buried power rail structures over a substrate, using replacement silicide and interconnect processes that withstand high thermal conditions, allowing for the integration of 3D semiconductor devices by maintaining power and performance through the use of reverse or replacement silicide and interconnect materials that are initially implemented and then replaced after front-end-of-line anneals, enabling 3D logic architectures like CFET or FINFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high thermal processing is applied to semiconductor devices, then transistor density and device performance can be improved, but metal gate materials are damaged and threshold voltage shifts occur
Solution Approach 1:
A replacement metal gate material is introduced as an intermediary that can withstand high thermal processing temperatures without damage. This replacement gate serves as a protective mediator during thermal annealing processes, allowing the actual metal gate to be formed later without experiencing thermal damage that would cause threshold voltage shifts.
Solution Approach 2:
The replacement metal gate is formed in advance before high thermal processing steps. This preliminary action ensures that the gate structure is already in place and protected during subsequent thermal annealing, dopant activation, and other high-temperature processes, preventing threshold voltage instability.
2Manufacturing precision
If wire pitch scaling is reduced to increase transistor density, then 3D integration can be achieved, but resistance and capacitance increase leading to reliability concerns
Solution Approach 1:
The patent transitions from two-dimensional planar scaling to three-dimensional vertical stacking of transistors. By stacking multiple transistor layers vertically, the design achieves higher transistor density without further reducing wire pitch, thereby maintaining signal integrity and avoiding the resistance and capacitance penalties associated with aggressive pitch scaling.
3Reliability
If replacement silicide and interconnect processes are used to maintain thermal processing integrity, then device performance is preserved, but process complexity increases
Solution Approach 1:
The patent employs replacement metal gate and silicide processes that involve changing material parameters at different fabrication stages. Replacement materials are introduced temporarily to withstand high-temperature processing, then swapped for final materials. While this adds process steps, it enables thermal processing integrity and can be integrated into existing fabrication workflows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the continuation of semiconductor scaling by maintaining high thermal processing integrity, reducing contact resistance, and preserving device performance and power efficiency, while allowing for the integration of complex 3D logic devices by using replacement silicide and interconnect processes that support high thermal requirements.
Implementation Method 1
A thermal process can be executed for the first wafer
Data Source
AI summary
A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.