Reverse Damascene Metallization for Etching Defect Reduction
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Solution Overview
Problem
The dual damascene process for forming back-end-of-the-line metallization layers in integrated chips is prone to etching defects such as under-etching, over-etching, facet defects, and voids, which negatively affect the reliability of metal interconnect wires due to challenges in photoresist plug formation and dielectric material etching.
Innovation Solution
A reverse damascene process is employed, where freestanding metal layer structures are formed within a patterned photoresist layer, followed by deposition of a diffusion barrier layer and inter-level dielectric material, and subsequent planarization to remove excess material, thereby avoiding etching-related defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a photoresist plug is formed to a height that is too high to prevent metal line trench from further etching the underlying via hole, then the via hole is protected from over-etching, but the dielectric material may be under-etched leaving fence defects
Solution Approach 1:
The patent inverts the traditional dual damascene sequence by first forming the metal line trench and then forming the via hole through the bottom of the trench. This reversal eliminates the need for photoresist plugs and avoids the under-etching/fence defects problem entirely, as the via hole is formed after the trench etching is complete
Solution Approach 2:
The patent performs preliminary actions by first depositing the metal layer and forming the trench, then subsequently forming the via hole. This preliminary formation of the trench structure before via hole creation allows precise control of the via hole etching without affecting the already-formed trench
2Manufacturing precision
If a photoresist plug is formed to a height that is too low to allow metal line trench etching, then the dielectric material can be fully etched, but the metal line trench may further etch the underlying via hole causing over-etching
Solution Approach 1:
The patent reverses the traditional sequence by forming the via hole after the metal line trench is already etched. This inversion ensures that the via hole etching cannot affect the trench, as the trench structure is already in place and the via hole is formed through the bottom of the trench in a separate, controlled step
3Ease of manufacture
If etching is performed to form metal line trench and via hole, then the metallization structures are created, but etching may damage the dielectric material during PR stripping or enhance nodule shape caused by standing waves
Solution Approach 1:
The patent inverts the traditional process by forming the via hole after the trench is etched, rather than before. This reversal eliminates the need for photoresist plugs and the associated standing wave effects that cause nodule formation, as the via hole is formed in a separate etching step through the bottom of the existing trench
Solution Approach 2:
The patent extracts and eliminates the photoresist plug formation step from the process sequence. By removing this intermediate step, the harmful standing wave effects and associated nodule defects are eliminated, while the metallization structures are still successfully formed through the inverted sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces etching problems and enhances the reliability of metal interconnects by forming metal structures before dielectric material deposition, resulting in improved quality and consistency of back-end-of-the-line metallization layers.
Implementation Method 1
A diffusion barrier layer is deposited onto the substrate which conforms to top and side surfaces of the metal layer structures
Implementation Method 2
An inter-level dielectric material is deposited onto the substrate to fill areas between metal layer structures
Implementation Method 3
the substrate is planarized to remove excess metal and inter-level dielectric material and to expose the top of the metal layer structures
Data Source
AI summary
The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.