Reverse Directory Segmentation for Cache Power Reduction

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Solution Overview

Problem

In multiprocessor systems, the power consumption of reverse directories increases significantly due to frequent updates and broadcasts across cache hierarchies, straining bus resources and degrading performance.

Innovation Solution

Implementing a reverse directory system with segregated sub-directories for high-frequency and low-frequency accesses, where only the relevant sub-directories are updated during write operations, reducing power consumption by writing to half of the directory entries during each update.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If reverse directory updates are performed for all cache lines during write operations, then cache coherency is maintained, but power consumption increases significantly

Engineering Contradiction:
Improvecache coherencyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The reverse directory is divided into multiple independent sub-directories (first reverse sub-directory and second reverse sub-directory), each handling different types of cache lines. This segmentation allows selective updating of only the relevant sub-directory during write operations, reducing power consumption while maintaining cache coherency for the affected cache lines.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different sub-directories are assigned different update policies based on their specific characteristics. The first reverse sub-directory is updated during write operations, while the second reverse sub-directory is updated only during invalidation operations. This local differentiation optimizes power consumption by updating only the necessary portions of the reverse directory.

Inventive Principle:
Principle #3Local quality

2Reliability

If broadcast messages are sent across the cache data bus for every cache update, then cache coherency is maintained, but bus resources are strained and performance degrades

Engineering Contradiction:
Improvecache coherencyVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts and eliminates unnecessary broadcast messages by implementing selective updating based on the reverse directory segmentation. Only the specific sub-directory containing the affected cache line is updated, and no broadcast is sent to other caches unless necessary. This reduces bus traffic and improves system performance while maintaining coherency.

Inventive Principle:
Principle #2Taking out (Extraction)

3Loss of information

If the entire reverse directory is updated during each write operation, then all cache line information is current, but only a percentage of entries actually need updating

Engineering Contradiction:
Improvedirectory information accuracyVSAvoidpower consumption
Core Design Contradiction:
Loss of informationVSLoss of energy

Solution Approach 1:

The reverse directory is segmented into multiple sub-directories, allowing the system to update only the specific sub-directory containing the modified cache line rather than the entire directory. This maintains information accuracy for affected entries while avoiding unnecessary power consumption from updating unrelated entries.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of performing a full directory update (excessive action), the patent implements partial updates limited to only the necessary sub-directory. This partial action is sufficient to maintain information accuracy for the modified cache lines while significantly reducing power consumption.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9720834B2Power saving for reverse directory
Publication Date: 2017.08.01 ORACLE INT CORP
  • US9720834B2 patent drawing
  • US9720834B2 patent drawing
  • US9720834B2 patent drawing

AI summary

Embodiments include systems and methods for improving power consumption characteristics of reverse directories in microprocessors. Some embodiments operate in context of multiprocessor semiconductors having cache hierarchies in which multiple higher-level caches share lower-level caches. Lower-level cache is coupled with reverse directories associated with respective ones of the higher-level caches. Each reverse directory can be segregated into two reverse sub-directories, one reverse sub-directory for relatively high-frequency accesses (e.g., updating “valid” and/or “private” information), and the other reverse sub-directories for relatively low-frequency accesses updating “index” and “way” information). During a write mode operation, when the reverse directories are updated, the write operation is performed only on the sub-directories having the entries invoked by the update, such that write operations can frequently consume only a fraction (e.g., halt) of the power of a conventional reverse directory write operation.