Reverse Donut Model for IC Timing Analysis
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Solution Overview
Problem
Current timing analysis methods for integrated circuit (IC) designs face challenges in generating accurate timing constraints at lower level blocks due to hierarchical models, leading to incomplete and inaccurate performance analysis, and are inefficient when using flat level models.
Innovation Solution
A reverse donut model (RDM) is generated for IC blocks, preserving connectivity information of outer input-output pin layers and external circuit elements, allowing for faster and more accurate timing analysis by acting as a blackbox, reducing the need for block-level timing constraints and enabling design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If timing analysis is performed using hierarchical models with timing constraints, then analysis speed is improved, but timing accuracy at lower level blocks deteriorates
Solution Approach 1:
The patent segments the IC design into hierarchical blocks while creating a specialized reverse donut model for selected blocks. This model divides the block into an outer boundary layer (retained) and internal circuitry (removed), preserving only essential connectivity information. This segmentation allows timing analysis to proceed efficiently at the block level while maintaining accuracy for critical interface timing.
Solution Approach 2:
The patent creates a reverse donut model as a simplified copy of the original block, replacing the full hierarchical block with a pruned version that retains only outer boundary pins and their connectivity to external storage elements. This copy preserves essential timing characteristics while reducing complexity, enabling accurate timing analysis without the computational burden of full flat-level modeling.
2Measurement precision
If timing analysis is performed using flat level models, then timing accuracy is improved, but analysis time increases significantly
Solution Approach 1:
The patent extracts only the essential elements needed for accurate timing analysis - specifically the outer boundary pins and their connectivity paths to external storage elements - while removing unnecessary internal circuitry. This extraction creates a streamlined model that captures critical timing information without the computational overhead of complete flat-level modeling, achieving accuracy-efficiency balance.
Solution Approach 2:
Instead of the traditional approach of keeping internal details and removing external connections, the patent inverts the model by retaining outer boundary connectivity and removing internal circuitry. This reverse donut model approach prioritizes interface timing accuracy while minimizing model complexity, enabling fast analysis with high precision for critical paths.
3Productivity
If hierarchical models are used for timing analysis, then analysis efficiency is improved, but the ability to adjust for skew due to storage element locations deteriorates
Solution Approach 1:
The reverse donut model acts as an intermediary between full hierarchical and complete flat-level models. It provides the storage element location information needed for skew adjustment while maintaining the efficiency of hierarchical analysis. The model serves as a mediator that delivers critical timing information without requiring the computational resources of complete flat-level modeling.
Data Source
AI summary
A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified from the single level flat model of the IC. The pruning algorithm is further used to initialize a timer and to define timing constraints associated with each of a plurality of input and output pins associated with the identified block. A RDM for the identified block is generated by identifying and including connectivity information associated with a plurality of input and output pins in an outer boundary of the identified block and at least one layer of interface connection between each of the plurality of input and output pins in the outer layer of the identified block and one or more circuit elements external to the identified block in the IC interfacing with each of the plurality of input and output pins in the identified block. The generated RDM acts as a blackbox for the identified block and is used in place of the identified block for running the timing analysis.